A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analogue-todigital converters (SAR ADCs). Two split-junction binary-weighted capacitor arrays are used in a coarse/fine quantisation scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC.
猜您喜欢
推荐内容
开源项目推荐 更多
热门活动
热门器件
用户搜过
随便看看
热门下载
热门文章
热门标签
评论