CSE 675.02: Introduction to Computer Architecture
Designing
MIPS Processor
(Single-Cycle)
Presentation G
Reading Assignment: 5.1-5.4
Slides by Gojko Babić
Introduction
• We're now ready to look at an implementation of the system
that includes MIPS processor and memory.
• The design will include support for execution of only:
– memory-reference instructions:
lw
&
sw,
– arithmetic-logical instructions:
add, sub, and, or, slt
&
nor,
– control flow instructions:
beq
&
j,
– exception handling:
illegal instruction
&
overflow.
• But that design will provide us with principles, so many more
instructions could be easily added such as:
addu, lb, lbu, lui,
addi, adiu, sltu, slti, andi, ori, xor, xori, jal, jr, jalr, bne, beqz,
bgtz, bltz, nop, mfhi, mflo, mfepc, mfco, lwc1, swc1,
etc.
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Presentation G
2
1
Single Cycle Design
• We will first design a simpler processor that executes each
instruction in only
one clock cycle time.
• This is not efficient from performance point of view,
since:
– a clock cycle time (i.e. clock rate) must be chosen such that
the longest instruction can be executed in one clock cycle
and
– that makes shorter instructions execute in one unnecessarily
long cycle.
• Additionally, no resource in the design may be used more than
once per instruction,
thus some resources will be duplicated.
• The singe cycle design will require:
– two memories (instruction and data),
– two additional adders.
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Presentation G
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Elements for Datapath Design
4
A L U c o n tr o l
overflow
Z e ro
ALU
ALU
r e s u lt
MemWrite
32
Address
32
32
Write
data
Read
data
Data
memory
g. Sign-extension unit
MemRead
e. Data memory unit
16
Sign
extend
32
32
32
PC
32
32
32
a . P ro g ra m c o u n te r
c. ALU
MemRead=1
MemWrite =0
5
Read
register 1
Read
register 2
Reg isters
W rite
register
W rite
d ata
32
32
32
Data
32
Read
data 2
32
In s tru c tio n
m em ory
A dd
S um
In s tru c tio n
32
In s tr u c tio n
address
32
32
Shift
Left 2
32
Register
num bers
5
Read
data 1
5
32
Data
RegWrite
d. A d d e r
f . In st ru c tio n m e m o r y
h. Shift left 2
b . Register File
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Presentation G
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2
Abstract /Simplified View (1
st
look)
Data
Register #
PC
Address
Instruction
memory
Instruction
Registers
Register #
Register #
Data
Data
memory
ALU
Address
• This generic implementation:
– uses the program counter (PC) to supply instruction
address,
– gets the instruction from memory,
– reads registers,
–
babic
the instruction opcode to decide exactly what to do.
5
uses
g.
Presentation G
Abstract /Simplified View (2
nd
look)
Figure 5.1
•
PC is incremented by 4 by most instructions, and 4 +
4×offset by branch instructions.
•
Jump instructions change PC differently (not shown).
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Presentation G
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3
Our Implementation
•
•
An edge triggered methodology
Typical execution:
–
read contents of some state elements at the beginning of the clock
cycle,
–
send values through some combinational logic,
–
write results to one or more state elements at the
end
of the clock
cycle.
State
element
1
State
element
2
Combinational logic
Figure 5.5
Clock cycle
•
An edge triggered methodology allows a state element to be read
and written in the same clock cycle.
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Presentation G
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Incrementing PC & Fetching Instruction
A d d
4
R e a d
P C
a d d r e s s
I n s tr u c t io n
I n s t r u c tio n
Clock
m e m
o r y
Figure 5.6
with addition in red
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Presentation G
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4
Datapath for R-type Instructions
Clock
R e g W r ite
ALU control
I
25-21
R e a d
re g is te r 1
R e a d
d a ta
R e a d
Z e ro
I n s t r u c t io n
re g is te r 2
R e g is te r s
A L U
A L U
r e s u lt
R e a d
d a ta
W r it e
d a ta
2
1
4
I
20-16
I
15-11
W r it e
re g is te r
31
26 25
21 20
16 15
11 10
6 5
0
R-type
g. babic
000000
rs
rt
rd
00000
funct
Presentation G
add = 32
sub = 34
slt = 42
and = 36
or = 37
nor = 39
9
Complete Datapath for R-type Instructions
Based on contents of op-code and funct
fields,
Control Unit sets ALU control
appropriately and asserts RegWrite, i.e.
RegWrite = 1.
Add
Clock
4
R e g W r ite
I
25-21
Read
PC
address
R e a d
re g is te r 1
R e a d
d a ta
1
4
ALU control
I
20-16
Instruction
R e a d
re g is te r 2
R e g is te r s
Z e ro
A L U
A L U
r e s u lt
R e a d
I
15-11
Instruction
W r ite
re g is te r
d a ta
2
clock
memory
W r ite
d a ta
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Presentation G
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5
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