NVIDIA RISC-V Story
4
th
RISC-V Workshop 7/2016
Outlines
Introduce NVIDIA falcon CPU
Why a new CPU?
Introduce NV-RISCV
NVIDIA Falcon overview
Falcon =
FAst Logic CONtroller
Introduced over 10 years ago, and
used in >15 different hardware
engines today
Design for flexibility
Design for long memory latency
Design for low area
Design for security
priv
1
priv
2
ext
CSB
FALCON
Secure
bus
csb
RSA/ECC
SHA
csb
scp-cmd
i/f
AES
IMEM
CFG
BUS
ICD
int
CSB
pf1
pf2
ifetch
dec
ex
wb
PIPE
DMA
DMEM
dma to
FBIF
EMEM IF
ext mem
bus
interru
pts
vectored
IRQ
MISC
TMR
PIC
MTHD
CTXSW
ctsw to
FBIF
ext
IRQ to
IRQ
host
ptimer from
host
methods from
host
ctxsw from
host
Why Falcon Next Gen?
New use cases requiring more horsepower & feature
Wide addressing range
More performance
Not limit to code size
Rich OS support
Falcon has limits
Small addressing range
Poor performance (0.67DMIPS/Mhz, 1.4Coremark/Mhz)
No D$
No rich OS support
Falcon Next Gen – Options
Buy
ARM (A,R family)
Synopsys (ARC family)
MIPS
Cadence
Build
Improve falcon
Move to a new ISA (And this is when RISC-V came into the picture..)
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