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Z-scale - Tiny 32-bit RISC-V Systems - Yunsup Lee, Albert Ou, Albert Magyar

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risc-v

Z-scale  -  Tiny  32-bit  RISC-V  Systems  -  Yunsup  Lee,  Albert  Ou,  Albert  Magyar

Z-scale:
Tiny 32-bit RISC-V Systems
With Updates to the Rocket Chip Generator
Yunsup Lee, Albert Ou, Albert Magyar
2
nd
RISC-V Workshop
yunsup@eecs.berkeley.edu
6/30/2015
1
What is Z-scale? Why?
§ 
Z-scale is a tiny 32-bit RISC-V core generator
suited for microcontrollers and embedded
systems
§ 
Over the past months, external users have
expressed great interest in small RISC-V cores
§ 
Z-scale is designed to talk to AHB-Lite buses
- plug-compatible
with ARM Cortex-M series
§ 
Z-scale generator also generates the
- So
we have listened to your feedback!
interconnect between core and devices
- Includes
buses, slave muxes, and crossbars
2
Berkeley’s RISC-V Core Generators
§ 
Z-scale:
Family of Tiny Cores
- Similar
in spirit to
ARM Cortex M0/M0+/M3/M4
- Integrates
with AHB-Lite interconnect
§ 
Rocket:
Family of In-order Cores
- Currently
64-bit single-issue only
- Plans
to work on dual-issue, 32-bit options
- Similar
in spirit to
ARM Cortex A5/A7/A53
- Will
integrate with AXI4 interconnect
§ 
BOOM:
Family of Out-of-Order Cores
- Supports
64-bit single-, dual-, quad-issue
- Similar
in spirit to
ARM Cortex A9/A15/A57
- Will
integrate with AXI4 interconnect
- BOOM
talk right after this one
3
Z-scale Pipeline
PC
Gen.
IF
DE
EX
WB
MEM
MUL
D-Bus
Response
I-Bus
Request
I-Bus
Response
D-Bus
Request
§ 
32-bit 3-stage single-issue in-order pipe
§ 
Executes RV32IM ISA, has M/U privilege modes
§ 
I-bus and D-bus are AHB-Lite and 32-bits wide
§ 
Interrupts are supported
§ 
Will publish a “microarchitecture specification”
4
ARM Cortex-M0 vs. Z-scale
Category
ISA
Architecture
Performance
Process
Area Efficiency
Frequency
Voltage (RTV)
Dynamic Power
ARM Cortex-M0
32-bit ARM v6
0.87 DMIPS/MHz
TSMC 40LP
124 DMIPS/MHz/mm
2
≤50
MHz
1.1 V
5.1 µW/MHz
RISC-V Zscale
32-bit RISC-V (RV32IM)
1.35 DMIPS/MHz
TSMC 40GPLUS
0.0098 mm
2
138 DMIPS/MHz/mm
2
~500 MHz
0.99 V
1.8 µW/MHz
Single-Issue In-Order 3-stage Single-Issue In-Order 3-stage
Area w/o Caches 0.0070 mm
2
§ 
Note: numbers are very likely to change in the future as we tune the
design and add things to the core.
5
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