Static Timing Analysis for
Nanometer Designs
A Practical Approach
J. Bhasker
•
Rakesh Chadha
Static Timing Analysis for
Nanometer Designs
A Practical Approach
J. Bhasker
eSilicon Corporation
1605 N. Cedar Crest Blvd.
Suite 615
Allentown, PA 18103, USA
jbhasker@esilicon.com
Rakesh Chadha
eSilicon Corporation
890 Mountain Ave
New Providence, NJ 07974, USA
rchadha@esilicon.com
ISBN 978-0-387-93819-6
e-ISBN 978-0-387-93820-2
DOI: 10.1007/978-0-387-93820-2
Library of Congress Control Number: 2009921502
Springer Science+Business Media, LLC 2009
All rights reserved. This work may not be translated or copied in whole or in part without
the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring
Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or
scholarly analysis. Use in connection with any form of information storage and retrieval,
electronic adaptation, computer software, or by similar or dissimilar methodology now
known or hereafter developed is forbidden. The use in this publication of trade names,
trademarks, service marks and similar terms, even if they are not identified as such, is not to
be taken as an expression of opinion as to whether or not they are subject to proprietary
rights.
While the advice and information in this book are believed to be true and accurate at the
date of going to press, neither the authors nor the editors nor the publisher can accept any
legal responsibility for any errors or omissions that may be made. The publisher makes no
warranty, express or implied, with respect to the material contained herein.
Some material reprinted from “IEEE Std. 1497-2001, IEEE Standard for Standard Delay
Format (SDF) for the Electronic Design Process; IEEE Std. 1364-2001, IEEE Standard
Verilog Hardware Description Language; IEEE Std.1481-1999, IEEE Standard for
Integrated Circuit (IC) Delay and Power Calculation System”, with permission from IEEE.
The IEEE disclaims any responsibility or liability resulting from the placement and use in
the described manner.
Liberty format specification and SDC format specification described in this text are
copyright Synopsys Inc. and are reprinted as per the Synopsys open-source license
agreement.
Timing reports are reported using PrimeTime which are copyright © <2007> Synopsys, Inc.
Used with permission. Synopsys & PrimeTime are registered trademarks of Synopsys, Inc.
Appendices on SDF and SPEF have been reprinted from “The Exchange Format Handbook”
with permission from Star Galaxy Publishing.
Printed on acid-free paper.
springer.com
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
C
HAPTER
1:
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
Nanometer Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
What is Static Timing Analysis?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Why Static Timing Analysis? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Crosstalk and Noise, 4
1.5
1.6
1.7
1.8
1.9
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.1
CMOS Digital Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.2
FPGA Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.3
Asynchronous Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STA at Different Design Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Limitations of Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reliability Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Outline of the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
C
HAPTER
2:
STA Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1
CMOS Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1
Basic MOS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2
CMOS Logic Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.3
Standard Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Modeling of CMOS Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Switching Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
v
2.2
2.3
C
ONTENTS
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Propagation Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slew of a Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Skew between Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Arcs and Unateness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Min and Max Timing Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
28
30
33
34
36
39
C
HAPTER
3:
Standard Cell Library . . . . . . . . . . . . . . . . . . . . . . . 43
3.1
3.2
Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2.1
Linear Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.2
Non-Linear Delay Model. . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Example of Non-Linear Delay Model Lookup, 52
3.3
3.2.3
Threshold Specifications and Slew Derating. . . . . . . . . . . . 53
Timing Models - Combinational Cells . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.1
Delay and Slew Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Positive or Negative Unate, 58
3.4
3.3.2
General Combinational Block . . . . . . . . . . . . . . . . . . . . . . . 59
Timing Models - Sequential Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.1
Synchronous Checks: Setup and Hold. . . . . . . . . . . . . . . . . 62
Example of Setup and Hold Checks, 62
Negative Values in Setup and Hold Checks, 64
3.4.2
Asynchronous Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Recovery and Removal Checks, 66
Pulse Width Checks, 66
Example of Recovery, Removal and Pulse Width Checks, 67
3.5
3.6
3.7
3.4.3
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
State-Dependent Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
XOR, XNOR and Sequential Cells, 70
Interface Timing Model for a Black Box . . . . . . . . . . . . . . . . . . . . . . 73
Advanced Timing Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.7.1
Receiver Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Specifying Capacitance at the Pin Level, 77
Specifying Capacitance at the Timing Arc Level, 77
3.7.2
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
vi
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论