IP
Rick Kelly
2009
1
Synopsys
Soc
CDC
CDC
Synopsys DesignWare
DesignWare
•
•
•
•
•
•
— DW_sync
— DW_pulse_sync, DW_pulseack_sync
— DW_data_sync, DW_data_sync_na, DW_data_sync_1c
— DW_fifo_s2_sf, DW_fifo_2c_df, DW_stream_sync
— DW_reset_sync
— DW_data_qsync_hl, DW_data_qsync_lh
1
Clk_d
Clk_d
0
1
2
0
1
Q
Clock to Q delay
FF Minimum specs
Q
2
MTBF
f
clk
f
data
t
res
T
0
T1
2
2
FF1
Q
FF2
MTBF
FPGA
2
3
1
3
FF2
3
3
Sampe MTBF test …
Error Counter
MTBF
MTBF
T0 T1
MTBF
T0 T1
4
4
MTBF
•
Debora Grosse, Unisys,
EDN,
1994
http://www.edn.com/archives/1994/062394/13df2.htm
•
Kleeman & Cantoni,
IEEE Transactions on Computers,
ol. C-36, No. 1, Jan., 1987
•
Google:MTBF
5
1/2
1
2
5a
–
1
2
5b
–
1/2
1
2
5c
–
D
1/2
5
DesignWare
DW_sync
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