W86L388
Programming Information
6. REGISTER
The register in the W86L388 is direct access registers and indirect access registers. The direct access
registers and indirect access registers are listed as follows:
Addr
A[3:1]
Register Name
(note 1)
Content (note 2)
B B B B
9
8
7
6
B
15
B
14
B
13
B
12
B
11
B
10
B
5
B
4
B
3
B
2
B
1
B
0
Direct Access Registers:
000
Command Pipe Reg.
(WO)
Response Reg. (RO)
001
Status Reg. (RO)
001
010
010
011
011
100
100
101
101
110
111
Control Reg. (R/W)
Receive Data Buffer
(R/O)
Transmit Data Buffer
(WO)
Interrupt Status Reg.
(RC)
Interrupt Enable Reg.
(R/W)
General I/O Port Data
Reg. (
R/W)
General I/O Port
Control Reg. (
R/W)
General IP Interrupt
Status Reg. (
RC)
General IP Interrupt
Enable Reg. (
R/W)
Index Address Reg.
(
R/W)
Index Data Register
0
0
0
Command pipe registers / Response registers
0
0
0
0
0
0
0
0
0
0
Status
0
1
-
-
-
0
-
0
-
0
-
0
0
X
-
-
-
-
-
0
-
0
-
0
-
0
-
0
-
0
-
0
X
0
-
0
X
0
-
0
-
0
-
0
-
-
0
-
-
X
Indirect Access Registers:
000
Extend Status Reg.
(RO)
000
Setting Reg. (R/W)
001
010
011
Data Format Register
(R/W)
Nac Time-out Register
(R/W)
Error Status Reg. (RO)
X
0
0
Receive data buffer
0
0
0
0
0
0
0
0
Transmit data buffer
X X X X X X X X
Interrupt status
-
-
0
0
0
0
0
0
-
-
-
-
-
-
0
0
GIO data
-
-
0
X X X X X
-
-
-
-
-
-
0
0
GIO interrupt status
-
-
0
0
0
0
0
0
-
-
-
-
-
-
0
0
-
-
-
-
-
-
0
0
Index data register
X X X X X X X X
Extend status
0
0
0
0
-
-
-
-
-
0
1
-
0
-
0
-
0
-
-
Control
0
0
0
X
-
0
X
-
0
0
X
-
1
0
X
-
0
0
X
-
Interrupt enable
0
0
0
1
-
-
-
-
1
-
0
-
0
-
0
-
GIO control
0
0
0
-
-
-
0
-
GIO interrupt enable
0
0
0
0
0
0
Index address
0
0
0
0
0
0
X
-
X
-
X
-
X
-
X
-
X
-
0
-
W
0
0
0
-
-
0
1
0
1
1
Status
Setting register
0
0
1
0
0
0
Data length
0
0
0
0
0
0
0
0
0
Nac time out register
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
0
0
1
-
1
0
1
-
0
100
0
0
Ready & Data Size
Register (R/W)
0
0
0
0
0
0
Note 1: R/W means the register can be read and write.
RO means the register is read only.
RC means the register is read only and read clear.
WO means the register is write only.
Note 2: The data bit in the content is the initial value during hardware reset.
0: the bit value is 0.
1: the bit value is 1.
X: the bit value is unknow.
-: Undefined bit in the register and the value will read 0.
0
0
Test
0
0
0
0
0
F
0
-
0
-
0
-
0
-
0
-
0
-
0
8-
0
6.1 Register Description
6.1.1 Direct Access Registers
Command Pipe Register A[3:1] = 000, Write only:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
Command pipe registers
Bit 47 Bit 46 Bit 45 Bit 44 Bit 43 Bit 42 Bit 41 Bit 40 Bit 39 Bit 38
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 37 Bit 36 Bit 35 Bit 34 Bit 33 Bit 32
Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
1
The 48-bit of SD command is located at the 3 words of command pipe, the Host must write three
words continuously, the first write word is bit 47 to bit 32 of the command, the second write word is
bit 31 to bit 16, the third word is bit 15 to bit 1, bit 0 of the command is 1 always. The 7-bit CRC
code is located at bit [7:1] of command, these bits are ignored and the CRC code will generated
automatically if the CMD_CRC bit in the setting register is enabled. The command will not started
until the three word of the register has been written. When the CMD12 write to the command pipe
register, the time period from the first word write action to the end of third word write action must
longer than the clock period of the system clock.
These registers will be cleared during hardware or software reset.
When the CPU data size is 8-bit, the 48-bit of SD command is located at the 6 bytes of command
pipe, the Host must write six bytes continuously. If the 7-bit CRC code is generated automatically,
the last byte also must write but the content of this byte is ignored.
Response Register A[3:1] = 000, Read only:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
48-bit respnse registers
Bit 47 Bit 46 Bit 45 Bit 44 Bit 43 Bit 42 Bit 41 Bit 40 Bit 39 Bit 38
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
136-bit respnse registers
0
0
0
0
0
0
0
0
Bit
Bit
135
134
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
127
126
125
124
123
122
121
120
119
118
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
111
110
109
108
107
106
105
104
103
102
Bit 95 Bit 94 Bit 93 Bit 92 Bit 91 Bit 90 Bit 89 Bit 88 Bit 87 Bit 86
Bit 79 Bit 78 Bit 77 Bit 76 Bit 75 Bit 74 Bit 73 Bit 72 Bit 71 Bit 70
Bit 63 Bit 62 Bit 61 Bit 60 Bit 59 Bit58 Bit 57 Bit 56 Bit 55 Bit 54
Bit 47 Bit 46 Bit 45 Bit 44 Bit 43 Bit 42 Bit 41 Bit 40 Bit 39 Bit 38
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 37 Bit 36 Bit 35 Bit 34 Bit 33 Bit 32
Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
1
Bit 5
Bit
133
Bit
117
Bit
101
Bit 85
Bit 69
Bit 53
Bit 37
Bit 21
Bit 5
Bit 4
Bit
132
Bit
116
Bit
100
Bit 84
Bit 68
Bit 52
Bit 36
Bit 20
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Bit
Bit
131
130
129
128
Bit
Bit
Bit
Bit
115
114
113
112
Bit 99 Bit 98 Bit 97 Bit 96
Bit 83
Bit 67
Bit 51
Bit 35
Bit 19
Bit 3
Bit 82
Bit 66
Bit 50
Bit 34
Bit 18
Bit 2
Bit 81
Bit 65
Bit 49
Bit 33
Bit 17
Bit 1
Bit 80
Bit 64
Bit 48
Bit 32
Bit 16
1
The 48-bit or 136-bit card response data may be read this register repeatedly, the first word is bit 47
to 32 of the response if the response is 48 bits, the first word is bit 135 to bit 128 at the data pin of bit
7 to 0 if the response if 136 bits.
These registers will be cleared during hardware or software reset.
Status Register A[3:1] = 001, Read only:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
INT DRQ R2 CMD_ Buf_ Buf_ DAT_ DAT_
-
RSP Epty Full
TX
RV
0
0
0
0
1
0
0
0
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
INT (Interrupt): This bit = 1 when the interrupt input becomes active (low) regardless any state of
INT_E bit of the interrupt enable register.
DRQ (DMA request): This bit = 1 when DMA request input (DRQN) becomes active (low).
R2 (R2 response): This bit reflects the data stored in the response registers are the R2 response and
136 bits effective. The 48-bit of response is stored if this bit = 0. This bit will updated if the card
response has been received and RSP bit (bit 12) of this register is active.
CMD_RSP (Card command response): This bit indicates that the response from the card has been
received and R2 status is updated. This bit will be cleared automatically if the Host read response
data.
Buf_Epty (Buffer empty): This bit = 1 when the command is receive data on the data line and the
receive data buffer is empty or when the command is transmit data on the data line and the transmit
data buffer is empty. The receive and transmit data buffer will set to empty during reset.
Buf_Full (Buffer full): This bit = 1 when the command is receive data on the data line and the receive
data buffer is full or when the command is transmit data on the data line and the transmit data buffer
is full.
DAT_TX (Data transmit): This bit indicates the data will transmit to the card on the data line. It will
reset to low when the command has been executed completedly.
DAT_RV (Data receive): This bit indicates the data receive from the card on the data line. It will set
high when the command pipe of read command has been write completedly and will reset to low
when the data length and CRC-16 has been received and the receive data buffer has been read out
completedly. In multi block read operation, this bit stays in high until the STOP_TRANSMISSION
command is written. The buffer status bits of Buf_Epty and Buf_Full reflect the status of receive data
buffer if this bit is high, the Buf_Epty and Buf_Full reflect the status of transmit data buffer if this bit
is low.
Bit [15:8] of this register will set to default value during hardware or software reset.
Control Register A[3:1] = 001, Read/Write:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
-
-
-
-
-
-
-
Bit 8 Bit 7 Bit 6 Bit 5
-
PWD RST DBF_
RST
0
0
0
Bit 4
SIEN
0
Bit 3
Bit 2 Bit 1
C_CLKS
0
1
Bit 0
0
0
PWD (Power down): This bit = 1 is used to power down the internal logic and crystal driver. Set this
bit to low will enabled the W86L388 when the W86L388 is in power down state. But the W86L388
will never enabled if Host interface type 2 is configured and the Host I/F clock (HCKI) input is
disabled.
RST (Reset): This bit = 1 is software reset and is used to reset the internal logic and receive and
transmit data buffer, the content of other registers are not affected. The command register pipe and
response registers will be cleared. This bit will return to low after software reset.
DBF_RST (Data buffer reset): This bit is used to reset the receive and transmit data buffer, it will
return to low automatically after the data buffer have been reset.
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