Avalanche Characteristics and Ratings of Power MOSFET
Giovanni Privitera
Product & Application engineering
Power MOSFET Division
STMicroelectronics
Catania Italy
1.1
Introduction
Source
Gate
D
C
Back in the mid 80's, power MOSFET manufacturers started to
claim a new outstanding feature: the Avalanche Ruggedness.
Suddenly, new families of devices evolved, all with this “new”
feature. The implementation was quite simple: the vertical
MOSFET structure has an integral body drain diode, which
cannot be eliminated. So, by changing some process and layout
parameters, it is possible to guarantee the use of the clamping
capability
of
this
diode
in
withstanding
accidental
Figure 1 MOSFET vertical structure and parasitic
elements
Figure 1 refers to the well known ST patented high voltage
MOSFET structure, MESH OVERLAY
TM
except some
process optimization of the shape of the body-drain junction
and other important improvements in the MESH overlay
design. The concept of this vertical structure could be
considered valid also for various older cellular or other
technologies.
During on state, while the gate source voltage is above the
threshold, the conduction current is localized in the drain and
in the region below the gate (channel). During off state the
Voltage drop across drain and source is sustained by the PN
junction at reverse bias, and a very small current (leakage)
flows through the junction.
If the voltage increases too much and the electrical field
reaches the critical value, the junction goes to breakdown, and
The basic and simplified vertical structure of a MOSFET is
drawn in Figure 1. The actual MOSFET is an infinite parallel
of these 'microscopic ' structures that work together sharing the
same
DRAIN,
with all the
GATEs
connected together by a
deposed polysilicon mesh and all the
SOURCEs
linked by the
top metal.
current starts to flow through the body region. So, if an over-
voltage is applied to the junction, a current flows through it
while the MOSFET limits the actual drain – source breakdown
voltage.
The breakdown mechanism itself, is not destructive for a p-n
junction. However, overheating caused by the large breakdown
current and high breakdown voltage damages the PN junction
unless sufficient heat sinking is provided.
voltage/power surges beyond the nominal drain source voltage,
Of course the confusion about the meaning of ruggedness, and
how to rate this in the datasheet was so huge, coupled with the
poor theoretical knowledge of it.
Despite this, all Power MOSFET manufacturers started to
produce avalanche rated devices, propose datasheet ratings
(although imperfect), to protect themselves and the end users,
from this incomplete knowledge.
Today, knowledge on device’s behavior during avalanche
conditions is enhanced. A lot of application notes and papers
were issued with different approaches to explain ratings and
avalanche behavior. The scope of this note is to briefly review
the MOSFET physics on avalanche to supply designers with
tools and hints to deal with avalanche issues.
P
+
P
N
-
N
+
Drain
G
R
p
S
1.2
MOSFET fundamentals
Avalanche characteristics and ratings of Power MOSFET
Looking at the structure of the MOSFET, one can see that the
PN junction is not a simple nor perfect diode. The diode of the
MOSFET is the collector base junction of a BJT (Bipolar
Junction Transistor, also called the parasitic transistor) made
by the N
+
region of source, P/P
+
region of the body and N
+
region of the drain, with the base shorted to the emitter by the
front metal.
The capability of a MOSFET to withstand avalanche condition
takes into account these two concerns. In fact, two kinds of
failure arise: one related to current, and the other to power
dissipation. In the former, failure is caused by the latching of
the parasitic bipolar due to the current that flows through its
base resistance, multiplied by the gain. The second is reached
when the temperature of the junction rises to a critical value
that provokes the formation of hot spots with average
temperatures about 650°C and peak of approximately 1000°C
caused by
regenerative thermal runaway, causing the
extremely rapid destruction of the device.
has been the first step for the improvement of the MOSFET,
followed by other more subtle optimizations.
The power that is dissipated in the MOSFET causes an
increase in junction temperature. If the temperature increases
to a critical value set by the property of the silicon [2], the
failure, without the contribution of the parasitic bipolar, occurs
because of the creation of thermally generated carriers in the
epitaxyal / bulk region and so the creation of hot spots.
The critical temperature to have this phenomenon is beyond
the maximum junction temperature of the devices and is
related to the intrinsic temperature of doped silicon, to which
the concentration of the bulk equals the one of the thermal
generated carriers.
The temperature increase during avalanche phenomena, due to
thermal capacitance of the silicon, is not instantaneous. Hence,
this kind of failure should be distinguished from that caused by
current as the device holds the breakdown voltage for a finite
time before destruction.
1.2.1 Failure Mode Descriptions
As previously discussed, the integral diode of a MOSFET is
the collector base junction of the parasitic transistor. If the
current flows laterally through region p, the increase in the
voltage drop across the emitter base resistance causes the BJT
to turn-on. The initial avalanche current is concentrated mainly
in the diode localized in the deep zone of p
+
; as soon as the
current grows, it begins to interest also the p, lighter doped,
regions. Since, by design, the value of lateral resistance Rp is
higher than the one of the vertical resistance of the heavy
doped p
+
region, and the current is concentrated in the region
p
+
, so the BJT should not turn on.
As soon as the current begins to interest the p region, causing a
sufficient drop of voltage to equal the VBE of the BJT, the
current of the base, Ib, in conjunction with the
β
of the
transistor will cause the BJT turn-on. VBE has a negative
temperature coefficient consequently leading to thermal
runaway and finally, the destruction of the device due to the
secondary breakdown of the parasitic BJT.
The adoption of a strongly doped P
+
region, determining the
reduction of the gain of the transistor and the base resistance
1.3
Testing the Avalanche Ruggedness
The Avalanche capability of the device is classically evaluated
by a circuit that performs an Unclamped Inductive Switching
(UIS) like the one described in Figure 2.
R
Figure 2 UIS reference diagram
The operation is the following; at zero time the device switches
on, closing the circuit. Due to the presence of an inductance,
(considering some resistance due to the layout and the ON
resistance of the MOSFET) the current increases following an
2
Avalanche characteristics and ratings of Power MOSFET
exponential law, as a function of the L / R characteristics of the
circuit.
energy to be withstood on the coil, but actually the only
recognized method (JEDEC standard No. 24-5,
MIL-
STD750D method 3040.2) is the circuit described in Figure 2.
L
+
VDD
-
ZENER
DUT
Figure 5 disconnected supply UIS fixture
A circuit commonly used to test the Avalanche ruggedness of
the MOSFET is shown in figure 5. It has a special feature of a
power switch in series to the VDD that connects the voltage
source to the circuit only during the coil charging,
disconnecting it a few microseconds before the switch-off and
the avalanche operation. This technique allows to increase the
Vdd beyond its maximum rated VDS, speeds up the charge of
the coil during turn on, and consequently decreases the turn on
state time. Also, the energy dissipated is different as one can
read in the table 1.
Figure 3 Typical UIS waveforms
As soon as the device is switched off, as the magnetic field in
the inductance cannot instantaneously go to zero, the di/dt
causes an over voltage on the drain of the device.
Naturally, the device is practically an open circuit up to its own
blocking voltage, therefore the extra voltage is limited by the
BVDSS of the DUT. During the avalanche, the current flows
through the DUT, dissipating the accumulated energy that was
stored in the coil during the charging. Table 1 explains several
relations for the tav, Eav and the Pavg with several circuit
configurations.
1.4
Datasheet Ratings
When the device is classified as “Avalanche Rated”, the
datasheet provides the end-user some useful parameters, which
define the ratings of the device during avalanche:
-Iar,
defined as the maximum current that can flow through the
device during the avalanche operations without any BJT
latching phenomenon. This Maximum limit must be considered
as an absolute maximum rating. Even if the critical current to
bring the device to failure is higher than the IAR, the producer
Figure 4 Constant current avalanche fixture
A device is commonly defined rugged, or avalanche-rated, if at
some stated conditions of coil and conducted current it
survives this test.
In the past, other circuits were suggested to test this device
capability like the one in Figure 4. The current is maintained
constant for a set time eliminating the dependency for the
guarantees the operation of the device below this limit.
Besides, it is usually tested for several microseconds. All
STMicroelectronics’ High Voltage Power MOSFET are tested
according to the Iar. All the avalanche operations (single event
or repetitive) below this current value can be considered safe
unless power dissipation issues.
It is important to underline that for MOSFETs connected in
3
Avalanche characteristics and ratings of Power MOSFET
parallel, the current that is switched during the avalanche
phenomenon is not shared, differently from the operations in
conduction state. In fact, at turn off, only the device with the
lower breakdown and/or with the faster switch will go into
avalanche, withstanding the total current that during the on
state is shared with the other MOSFETs in parallel. If such
current is more than the Iar, the device can fail. Even if the
energy associated to that event is very low, failure is due to the
activation of the MOSFET’s parasitic bipolar.
-EAS
(Energy during Avalanche for Single pulse) is defined as
the maximum energy that can be dissipated by the device
during a single pulse avalanche operation, (at the circuit
conditions described above), at the Iar and at the starting
junction temperature of 25°C, to bring the junction temperature
up to the maximum one stated in the absolute maximum
ratings. Of course, this value decreases as the starting junction
temperature increases. Usually in some datasheet an energy
derating curve called “Avalanche Energy vs starting Tj”, is
provided [figure 6].
All the single event avalanche operations below this Energy
value are considered safe for the device if the junction starting
Temperature is 25°C, switching a drain current less or equal to
Iar. If Tj>25°C, the end user can refer to the curve “Avalanche
Energy vs starting Tj”, to apply the right derating.
From the board analysis, we find that the device for such
power supply condition can experience a single pulse
avalanche operation. The measurements have shown that the
average junction temperature is 100°C, the peak drain current
switched during the avalanche is 4A and the energy that is
dissipated during that single avalanche operation is 0.24mJ.
To understand if the device is working within the ratings, we
have to check the switched current, comparing it to the Iar;
because the Id peak value is 4A and below the Iar, this first
rating is satisfied. Now, to understand if the junction
temperature is below the Tj max, we suppose that before the
avalanche the junction temperature is the average one, 100°C.
Looking at the plot “Avalanche Energy vs starting Tj”, the
energy to bring the junction temperature to the allowed
maximum rating, starting from 100°C, is approximately 50mJ.
Since the energy measured is below that value, the maximum
junction temperature reached during the avalanche will be less
than the Tj max. Considering that both the bonds, current
below Iar and
junction temperature
below maximum
temperature are well satisfied, one can safely state that the
device (under that single avalanche event) is working within
the ratings.
It is interesting to understand how this EAS value is set by
STMicroelectronics, also because each MOSFET manufacturer
states his/her own approach and findings.
In order to provide a
clear explanation, the EAS value is not simple to state, as it is
Id=Iar
very difficult to look at the junction temperature during the
avalanche operation.
Some manufacturers set this value by the thermal impedance
stated in the datasheet. This could be an interesting approach,
but some concerns would have to be taken into consideration.
The datasheet thermal impedance is the response of the system
to a rectangular power pulse, maintaining the package case at
25°C .
EAS @ Iar ,
Tj= 25°C
Starting Tj=100°C
Starting Tj
∆
T
jc
=
Zth
jc
(
t
)
P
ower
Figure 6 EAS vs temperature plot of STP9NK80Z
Example.
Let’s suppose to have an STP9NK80Z working as main switch
of a DC/DC converter. The datasheet ratings of this devices are
Eas=350mJ Iar=7.5A, Tj max=150°C
4
Avalanche characteristics and ratings of Power MOSFET
The application of the above mentioned formula without any
modification cannot give
precise information, in fact
considering two power pulses having the same peak, one
rectangular, the other triangular, we obviously find that the
peak temperature is quite different (figure 7). To use the Zth,
the triangular pulse can be approximated as rectangular with
scaled amplitude and width.
Tj(t)
P(t)
Triangular pulse and its response
Rectangular pulse and its
response
10
Id (Ampere)
1
good approximation in order to calculate the temperature
increase within the device during the avalanche operation if the
pulse has a short duration.
Starting from this model, the experimental verification is made
looking to the VDS shape during the Avalanche. In fact the
breakdown voltage of the device is not constant when varying
the temperature and the current [2].
100
time
Figure 7 Thermal response of triangular pulse
One more important concern about the use of thermal
impedance, is that usually it is experimentally and theoretically
calculated considering the on-state of the device and so a
power distribution within the device different from the one
during the avalanche-state.
STMicroelectronics’ approach to EAS statement starts from a
theoretical thermal model of the die with some experimental
verifications.
To calculate the maximum temperature in the junction during
Avalanche, an equation like the one below can be used [5]:
T
j
=
P
0
t
av
+
T
starting
AK
0.1
0
100
200
300
400
500
Vds (Volt)
600
700
800
900
1000
Figure 8 BVDSS vs ID
The variation of the blocking voltage with the current is nearly
linear and this resistance is specific of the die-size of a given
set of design rules, epitaxial layer and package. Figure 8 shows
the measured characteristic of BVDSS vs the Id for a 700V
device. The voltage variation with the temperature is positive
too, as shown in the datasheet plot, and the variation depends
on the structural characteristics of the silicon die.
By taking these into account, the junction temperature from the
VDS shape can be extrapolated.
eq. 1
Where
t
av
A
P
0
K
is the avalanche time (s)
die Area
(m
2
)
peak power (W)
silicon's thermal constant (Wm
-2
s
½
K
-1
)
It comes from the arrangement of the solution of the general
equation of heat transmission (Fourier equation), for the
special case of an infinite media (bi-dimensional case)
subordinated to a short rectangular power source pulse
uniformly distributed over an area [1].
The eq 1, applied to a triangular power pulse, is a simple and
Figure 9 Variation of VDS/ID shapes with the Coil during
the UIS
Fig 9 shows the real VDS shape during avalanche, where the
increase of VDS observed is due to the rise of the silicon
5
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