致尊敬的顾客
关于产品目½等资料中的旧公司名称
NEC电子公司与株式会社瑞萨科技于2010年4月1日进行业务整合（合并），整合后的
新公司暨“瑞萨电子公司”继承两家公司的所有业务。因此，本资料中½还保留有旧公司
名称等标识，½是并不妨碍本资料的有效性，敬请谅解。
瑞萨电子公司½址：http://www.renesas.com
2010年4月1日
瑞萨电子公司
【发行】瑞萨电子公司（
http://www.renesas.com）
【业务咨询】http://www.renesas.com/inquiry
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1.
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“Standard”:
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
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功率MOS
FET
结构与特点
瑞萨科技功率
MOS FET
具有
D
系列 （垂直结构）和
S
系列 （水平结构）
。其结构分别如图
1
和图
2
所示。
两者在特性上稍有差别，½½拥有功率
MOS FET
在本质上的优良特性，具½内容如下：
·
·
·
无½½流子的积累现象，具有优良的频率特性和开关特性。
无电流集中，破坏耐量大。
为电压控制器件，驱动功率小。
N
+
P
N
+
P
N
+
图
1 D
系列 （垂直）的结构 （N 沟道）
N
+
N
–
N
+
P
P
+
图
2 S
系列 （水平）的结构 （N 沟道）
为了解功率
MOS FET
的结构及特性，下面介绍一下基本的
N
沟道
MOS FET
结构和工½。
N
沟道
MOS FET
的基本结构如图
3
所示。因为控制电流的栅电极被氧化膜包围，所以该结构称为
MOS
结
构。源极指的是带电粒子 （这里为电子）源，漏极指的是电子的排出口。
如果对栅电极½加正电压，栅极正下方的
P
层就会反½½成沟道，并且漏极电流由漏极流向源极，这就是
MOS FET
的工½方式 （P 沟道与之相反）
。
如果在漏极
/
源极之间½加电压，沟道内的电子就向漏极移动，并产生漏极电流。
在栅极电压为
0V
时，产生漏极电流的FET 称为耗½型 （常开型）
，不产生漏极电流的
FET称为增强型
（常关型）
。瑞萨科技功率
MOS FET
全部为增强型 （常开型）
。
将漏极电流产生时的栅极电压称为栅极截止电压
V
GS(off)
（图
4）
。
通常
I
DS
−V
GS
为
2
次相关关系。该曲线的斜度为相互电导
gm(=ΔI
DS
/ΔV
GS
)，表示放大的尺寸。
RCJ27G0014-0100/Rev.1.00
February 2008
Page 1 of 6
功率
MOS FET
结构与特点
N
+
P
N
+
图
3 MOS FET
的基本结构 （N 沟道）
I
DS
Δl
DS
ΔV
GS
gm =
V
GS
0 V
GS (off)
Δl
DS
ΔV
GS
图
4
传输特性
漏极耐压由图
3
所示的漏极
N
+
区域和栅电极之间的结构决定。由于漏极
N
+
区域与栅电极的距离很近，中间
只隔着很薄的栅极氧化膜，这样会在两者之间产生强电场的集中，因此不½½成较强的漏极电压。普通
MOS
FET
的耐压值为
20
½
30V。
通过扩大该漏极
N
+
区域和栅电极的距离以缓和电场集中，可提高漏极耐压。此时，在漏极
N
+
区域和沟道
之间½成电流通路
N
层。
因此，高耐压
MOS FET可理解为在普通 MOS FET
的漏极端附加了电阻。
功率
MOS FET
为多个元件在内部并联的结构。
功率
MOS FET
的结构大致分为两种，一种称为
D
系列 （垂直结构）
，另一种称为
S
系列 （水平结构）其
结构如图
1
和图
2
所示。下面对各系列的结构及特点进行更详细的说明。
·
D系列
（垂直结构）
在
D
系列中漏极
N
+
区域½于硅电路板的下方。栅电极覆盖在沟道之间的整个
N
層上，以缓和栅极下方
的电场集中。
电子由源极水平穿过沟道到达
N
层。
此时，
栅电极的正电压在
N
层表面½成了
N
+
积累层，
电子在通过
N
+
积累层后，垂直穿过整个
N
层到达漏极。因此，将
D
系列称为垂直结构，并且外壳为漏
极。
由于保持漏极电压的部分（N 层）½于硅中，所以，D 系列的单个½积比
S
系列要小，并且，与相同电
压、相同芯片尺寸的
S
系列相比，
D
系列的通态电阻更小。
静电电容具有如图
5
所示的结电容和
MOS
电容。
因为栅极
/
漏极之间的电容
C
GD
比较大，因此不½½视
C
GD
对源极接地的输入电容
Ciss、输出电容 Coss
及反馈电容
Crss的½响。
Ciss=C
GS
+CGD
Coss=C
DS
+C
GD
Crss=C
GD
RCJ27G0014-0100/Rev.1.00
February 2008
Page 2 of 6
功率
MOS FET
结构与特点
Cgs
3
Cgs
1
N
+
P
Cds
1
N
+
Cgd
Cgs
2
N
+
P
Cds
2
R
DS
N
C
GS
=Cgs
1
+Cgs
2
+Cgs
3
C
DS
=Cds
1
+Cds
2
C
GD
=Cgd
图
5 D
系列 （垂直型）的结构 （N 沟道）
栅电极采用了在
CMOS LSI
中具有实际功效的多晶硅。多晶硅的电阻比铝或钼等金属材料高
100
倍左右，½
通过改进多晶硅栅与金属电极的连接后，降½了栅极电阻。在垂直结构中，因为反馈电容
Cgd
较大，并且漏极
电压的依存性较强，所以不½单纯由栅极电阻的时间常数来决定输入电容。这样，关于开关时间的工½分析变
得更为复杂。详细内容记½½于 《功率
MOS FET
½用时的注意事项》
。
·
S
系列 （水平结构）
在
S
系列中漏极
N
+
区域½于硅表面。在漏极
N
+
区域与沟道之间设½了
N
层，可½电场强度平均。而
且，½源电极扩展到了
N
层上面，可½为场板来防止栅极附近的电场集中。电子由源极水平穿过沟道
及
N
层到达漏极。因此，将
S
系列称为水平结构。为了½衬底保持一定的电½，将衬底连接到了源电
极，外壳为源极。
反馈电容
Crss
对应图
6
中的
Cgd。由于源极场板扩展到了 N
层上，因此可通过场板与
N
层的电容
Cds
来
屏½
Cgd，½得反馈电容 Crss的值非常小。
从芯片及封装两方面来看，
S
系列的结构适用于输入端与输出端分离的高频产品。
Cgs
N
+
Cgd Cds
R
DS
N
–
N
+
N
P
P
+
Csub
图
6 S系列
（水平型）的结构 （N 沟道）
RCJ27G0014-0100/Rev.1.00
February 2008
Page 3 of 6
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