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Synopsys Timing Constraints

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标签: Timing

Timing

Constraints

Constraints

VIVADO软件只能采用XDC约束了,XDC基于SDC

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Synopsys Timing Constraints and Optimization User Guide Version D201003 March 2010 Copyright Notice and Proprietary Information Copyright 2010 Synopsys Inc All rights reserved This software and documentation contain confidential and proprietary information that is the property of Synopsys Inc The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement No part of the software and documentation may ......

Synopsys
Timing Constraints and Optimization
User Guide
Version D-2010.03, March 2010
®
Copyright Notice and Proprietary Information
Copyright
©
2010 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary
information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and
may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may
be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise,
without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.
Right to Copy Documentation
The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only.
Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must
assign sequential numbers to all copies. These copies shall contain the following legend on the cover page:
“This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of
__________________________________________ and its employees. This is copy number __________.”
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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plus
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Service Marks (
SM
)
MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.
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ARM and AMBA are registered trademarks of ARM Limited.
Saber is a registered trademark of SabreMark Limited Partnership and is used under license.
All other product or company names may be trademarks of their respective owners.
Synopsys Timing Constraints and Optimization User Guide, version D-2010.03
ii
Contents
What’s New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.
Introduction to Synthesis Timing
Static Timing Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input and Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip-Flop and Latch Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Analysis in the Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synopsys Design Constraint (SDC) Commands . . . . . . . . . . . . . . . . . . . . . . . .
Library Timing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wire Load Models and Topographical Technology . . . . . . . . . . . . . . . . . . .
Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Retiming Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1-7
1-11
1-12
1-14
1-16
1-19
1-19
1-24
1-26
1-26
1-27
1-29
1-31
1-33
1-34
1-35
1-35
1-37
1-38
xiv
xiv
xvii
iii
Synopsys Timing Constraints and Optimization User Guide
Synopsys Timing Constraints and Optimization User Guide
Version D-2010.03
D-2010.03
Timing Analysis After Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesis Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.
Clocks
Creating Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Network Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagated Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Network Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Uncertainty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal Clock Transition Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Clock Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exclusive Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock-Gating Signal Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-by-2 Generated Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generated Clock Based on Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-by Clock Based on Falling Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shifting the Edges of a Generated Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combinational-Only Source Latency Calculation . . . . . . . . . . . . . . . . . . . . . . .
Generated Clock Based on a Non-Unate Master Clock . . . . . . . . . . . . . . . . . .
Estimated I/O Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculating I/O Latency for Input Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculating I/O Latency for Output Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.
Timing Paths
Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-39
1-40
2-2
2-3
2-5
2-5
2-6
2-7
2-8
2-11
2-12
2-12
2-14
2-16
2-16
2-18
2-22
2-24
2-29
2-30
2-30
2-31
2-33
2-34
2-35
2-37
2-39
2-40
2-40
3-2
Contents
iv
Synopsys Timing Constraints and Optimization User Guide
Version D-2010.03
User Grouping of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Weight or Cost Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Critical Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Specification Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Through Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rise/Fall From/To Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Path Delay Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Delay for Flip-Flops Using a Single Clock . . . . . . . . . . . . . . . . . . . . . . . . .
Path Delay for Flip-Flops Using Different Clocks . . . . . . . . . . . . . . . . . . . . . . . .
Setup Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hold Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Cycle Path Analysis Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
False Path Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum and Minimum Path Delay Exceptions . . . . . . . . . . . . . . . . . . . . . . . .
Multicycle Path Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Exceptions Efficiently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exception Order of Precedence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exception Type Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Path Specification Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reporting Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Removing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data-to-Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Data-to-Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generating Timing Reports for Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Checks and Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Library-Based Data Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.
Operating Conditions
Operating Condition Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Condition Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum and Maximum Delay Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Min-Max Cell and Net Delay Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3-2
3-3
3-3
3-4
3-5
3-6
3-9
3-9
3-11
3-12
3-12
3-13
3-15
3-16
3-17
3-18
3-23
3-25
3-25
3-25
3-27
3-27
3-28
3-29
3-31
3-32
3-32
4-2
4-4
4-5
4-7
4-7
Chapter 1: Contents
Contents
v
1-v
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