热搜关键词: 电路基础ADC数字信号处理封装库PLC

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H61主板原理图

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  • 2015-03-31
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标签: H61主板原理图

H61主板原理图

H61主板原理图,非常详细

5
4
3
2
1
D
C
B
01
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13
14
15
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COVER SHEET
CHANGE HISTORY
BLOCK DIAGRAM
CLOCK MAP
RESET MAP
GPIO MAP
POWER MAP
POWER SEQUENCE
MECHANIC
BLANK
MODULE_CLOCK
MODULE_SIO
MODULE_PS/2
MODULE_FAN
MODULE_FRONT PANEL
MODULE_HALO
MODULE_ATX POWER
MODULE_PCIE
MODULE_PCI
MODULE_SPI
MODULE_VGA/HDMI
MODULE_SATA
MODULE_USB
MODULE_LAN
MODULE_AUDIO
Model
Name:BLIZZARD
26
27
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31
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33
34
35
36
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38
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41
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44
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47
48
49
50
V1.0
D
MODULE_ESATA/PATA
MODULE_SSD
MODULE_BLUETOOTH
MODULE_DDR3 CHANNEL A
MODULE_DDR3 CHANNEL B
SANDY BRIDGE-1(MISC)
SANDY BRIDGE-2(PEGDMIFDI)
SANDY BRIDGE-3(MEMORY)
SANDY BRIDGE-4(POWER)
SANDY BRIDGE-5(GND)
COUGAR POINT-1(PCI)
COUGAR POINT-2(DMIUSBPCIE)
COUGAR POINT-3(SATA)
COUGAR POINT-4(GPIO)
COUGAR POINT-5(NVRAM)
COUGAR POINT-6(DISPLAY)
COUGAR POINT-7(FDI)
COUGAR POINT-8(CLOCK)
COUGAR POINT-9(POWER)
COUGAR POINT-10(GND)
VR_VCORE
VR_VAXG
VR_VTT
VR_DDR
VR_DISCRETE
C
B
A
A
Page Name
Size
C
ShenZhen Topstar Inductor Co.,Ltd
COVER SHEET
Project Name
1.0
Date:
Sheet
Friday, March 15, 2013
1
50
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5
4
3
2
1
F-H61
Rev
5
4
3
2
1
D
Model
V1.0
Name:BLIZZARD
DATE
Change Item
Reason
D
C
C
B
B
A
A
Page Name
Size
C
ShenZhen Topstar Inductor Co.,Ltd
CHANGE HISTORY
Project Name
1.0
Date:
Sheet
Friday, March 15, 2013
2
50
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5
4
3
2
1
F-H61
Rev
5
4
3
2
1
BLOCK DIAGRAM
D
VR12
Model
Name:BLIZZARD
LGA1155
D
CHA DIMM1
CHB DIMM2
PCI EXPRESS X16
FDI
DMI
C
C
PCI EXPRESS X1
PCI EXPRESS X1
VGA/HDMI
AUDIO
USB PORTS 10
SERIAL ATA 4
B
PCH
PCIE LAN
TPM
SPI BIOS
B
LPC
LPT
PS2
SIO
FRONT PANEL
FAN CONTROL
A
A
Page Name
Size
D
ShenZhen Topstar Inductor Co.,Ltd
BLOCK DISGRAM
Project Name
1.0
of
Date:
Sheet
Friday, March 15, 2013
3
50
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5
4
3
2
1
F-H61
Rev
5
4
3
2
1
D
D
Processor
CHA
CHB
TS_DBG
DMI/BCLK 100MHz
DMI
C
FDI
C
DMI/#
DP/#
CLKOUT_ITPXDP
PEG Gen 2X2 100MHz
PCH
CPU0/0#
CLKOUT_PEG_A:B/#
PCIE Graphics Slot
PCIE-e Gen 2.0 100MHz
SATA 100MHz
SRC & SATA/#
B
CLKIN_SATA_P/N
CK505
DOT 96 MHz
DOT96/#
CLKOUT_SRC7:0/7:0#
CLKIN_DOT96_P/N
PCIE
B
PCIE-e Gen 2.0
100MHz
SRC1/1#
CLKIN_DMI_P/N
PCI 33MHz loopback
CLKOUTPCILOOPBACK
SIO
SIO_48MHz
CLKOUTFLEX[3:0]
14/33/48/MHz X4
EC/TPM/etc
CLKOUTPCI_4:0
REF
REF 14.318MHz
REFCLK14IN
A
A
14.31818MHz
25.000MHz
Page Name
Size
D
ShenZhen Topstar Inductor Co.,Ltd
CLOCK MAP
Project Name
1.0
of
Date:
Sheet
Friday, March 15, 2013
4
50
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5
4
3
2
1
F-H61
Rev
5
4
3
2
1
D
Processor
RSTIN#
BUFFER
D
IDE
FWH
ATX
C
PWRGD_PS
PWROK Logic
C
PCH
PCIE
SIO
PLTRST#
B
B
FRONTPANEL
SYS_RESET#
PCIRST#
PWRBTN#
PWRON
PCI
Page Name
A
ShenZhen Topstar Inductor Co.,Ltd
RESET MAP
Size
A
Project Name
1.0
Friday, March 15, 2013
5
50
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5
4
3
2
1
F-H61
Rev
A
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