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xilinx公司_NEXYS3手册

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标签: NEXYS3

NEXYS3

xilinx公司_NEXYS3手册

Nexys3™ Board
Reference Manual
Revision: July 26, 2011
1300 Henley Court | Pullman, WA 99163
(509) 334 6306 Voice and Fax
Overview
The Nexys3 is a complete, ready-to-use
digital circuit development platform based on
the Xilinx Spartan-6 LX16 FPGA. The
Spartan-6 is optimized for high performance
logic, and offers more than 50% higher
capacity, higher performance, and more
resources as compared to the Nexys2’s
Spartan-3 500E FPGA. Spartan-6 LX16
features include:
2,278 slices each containing four 6-
input LUTs and eight flip-flops
576Kbits of fast block RAM
two clock tiles (four DCMs & two PLLs)
32 DSP slices
500MHz+ clock speeds
Adept USB2
Config & data
Cellular RAM
16MByte
47
23
4
USB HID Host
Mouse/Keyboard
2
Parallel PCM
Nonvolatile
Memory
16MByte
SPI PCM (x4)
Nonvolatile
Memory
16MByte
10/100
Ethernet PHY
8-bit VGA
Spartan-6
XC6SLX16
CSG324C
USB-UART
Clock 100MHz
8
22
Basic I/O
LEDs, Btns, Swts
40
28
32
10
High-Speed
Expansion
Pmod Port
Expansion
In addition to the Spartan-6 FPGA, the
Nexys3 offers an improved collection of
peripherals including 32Mbytes of Micron’s
latest Phase Change nonvolatile memory, a
10/100 Ethernet PHY, 16Mbytes of Cellular
RAM, a USB-UART port, a USB host port for
mice and keyboards, and an improved high-
speed expansion connector. The large FPGA
and broad set of peripherals make the
Nexys3 board an ideal host for a wide range
of digital systems, including embedded
processor designs based on Xilinx’s
MicroBlaze.
Nexys3 is compatible with all Xilinx CAD
tools, including ChipScope, EDK, and the
free WebPack. The Nexys3 uses Digilent's
newest Adept USB2 system that offers FPGA
and ROM programming, automated board
tests, virtual I/O, and simplified user-data
transfer facilities.
Xilinx Spartan-6 LX16 FPGA in a 324-pin BGA package
16Mbyte Cellular RAM (x16)
16Mbytes SPI (quad mode) PCM non-volatile memory
16Mbytes parallel PCM non-volatile memory
10/100 Ethernet PHY
On-board USB2 port for programming & data xfer
USB-UART and USB-HID port (for mouse/keyboard)
8-bit VGA port
100MHz CMOS oscillator
72 I/O’s routed to expansion connectors
GPIO includes 8 LEDs, 6 buttons,8 slide switches and
4-digit seven-segment display
USB2 programming cable included
A comprehensive collection of board support
IP and reference designs, and a large collection of add-on boards are available on the Digilent
website. Please see the Nexys3 page at
www.digilentinc.com
for more information.
Doc: 502-182
page 1 of 22
Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners.
Nexys3 Reference Manual
Configuration
After power-on, the Spartan-6 FPGA board must be configured (or programmed) before it can perform
any functions. The FPGA can be configured in one of four ways: a PC can use the Adept "USB Prog"
port to program the FPGA any time power is on; a configuration file stored in the non-volatile parallel
PCM device can be transferred to the FPGA at power-on using the BPI-UP port; a file stored in the
non-volatile serial (SPI) PCM device can be transferred to the FPGA using the SPI port; or a
programming file can be transferred from a USB memory stick attached to the USB HID port. An on-
board "mode" jumper (J8) selects between the programming modes as shown in the J8 Mode legend
in the figure below.
Programming files are stored in SRAM-based memory cells within the FPGA. This data defines the
FPGA’s logic functions and circuit connections, and it remains valid until it is erased by removing
board power, by pressing the reset button attached to the PROG input, or by writing a new
configuration file using the JTAG port.
FPGA configuration files transferred via the JTAG port use the .bin or .svf file types, files transferred
from a USB stick use the .bit file type, and BPI or SPI programming files can use .bit, .bin, or .mcs
types. The ISE/WebPack or EDK software from Xilinx can create bit, svf, bin, or mcs files from VHDL,
Verilog, or schematic-based source files (EDK is used for MicroBlaze™ embedded processor-based
designs). Digilent's Adept software or Xilinx's iMPACT software can be used to program the FPGA or
ROMs using the Adept USB port.
During JTAG programming, a .bit or .svf file is transferred from the PC to the FPGA using the Adept
USB port. When programming a non-volatile PCM device, a .bit, .bin, or .mcs file is transferred to the
in a two-step process. First, the FPGA is programmed with a circuit that can program PCM devices,
and then data is transferred to the PCM device via the FPGA circuit (this complexity is hidden from
the user – a simple “program ROM” interface is presented by the programming software. Note the
PCM devices are next-generation Flash ROM devices, and they are often referred to as "Flash" or
"ROM" memory). After the PCM device has been programmed, it can automatically configure the
FPGA at a subsequent power-on or reset event as determined by the J8 jumper setting. Programming
files stored in the PCM devices will remain until they are overwritten, regardless of power-cycle
events.
The FPGA can be programmed from a memory stick attached to the USB-HID port if the stick
contains a single .bit configuration file in the root directory, the J8 Programming Mode jumper is set to
Doc: 502-182
page 2 of 22
Nexys3 Reference Manual
JTAG (both jumpers loaded), and board power is cycled. The FPGA will automatically reject any .bit
files that are not built for the proper FPGA.
After being successfully programmed, the FPGA will cause the "Done" LED to illuminate. Pressing the
Reset button at any time will reset the configuration memory in the FPGA. After being reset, the
FPGA will immediately attempt to reprogram itself from one of the PCM devices if the J8 Mode jumper
is set to BPI or SPI mode.
Power
Jack
Power Select Power
Jumper
Good LED
Pmod
Connectors
Done
LED
JTAG
Header
Power
Switch
MODE
Jumper
Reset
Button
10/100
Ethernet
VHDC
Conncector
Adept
USB Port
VGA
Port
7-seg
Display
USB HID
Host Port
USB
UART
LEDs
Slide switches
Push buttons
Digilent's Adept software offers a simplified programming interface and many additional features as
described below. The Adept USB port is fully compatible with all Xilinx tools, including the iMPACT
programming software. The Adept features are always available, regardless of how the FPGA was
programmed.
Doc: 502-182
page 3 of 22
Nexys3 Reference Manual
Adept System
Digilent's Adept high-speed USB2 system can be used to program the FPGA and PCM devices, run
automated board tests, add PC-based virtual I/O devices (like buttons, switches, and LEDs) to FPGA
designs, and exchange register-based and file-based data with the FPGA. Adept automatically
recognizes the Nexys3 board and presents a graphical interface with tabs for each of these
applications. Adept also includes public APIs/DLLs so that users can write applications to exchange
data with the Nexys3 board at up to 38Mbytes/sec. The Adept application, an SDK, and reference
materials are freely downloadable from the Digilent website.
Programming Interface
To program the Nexys3 board using Adept, first
set up the board and initialize the software:
plug in and attach the power supply
plug in the USB cable to the PC and to
the USB port on the board
start the Adept software
turn ON Nexys3's power switch
wait for the FPGA to be recognized.
Use the browse function to associate the
desired .bit file with the FPGA, and click on the
Program button. The configuration file will be
sent to the FPGA, and a dialog box will indicate
whether programming was successful. The
configuration “done” LED will light after the
FPGA has been successfully configured.
Before starting the programming sequence, Adept ensures that any selected configuration file
contains the correct FPGA ID code – this prevents incorrect .bit files from being sent to the FPGA.
In addition to the navigation bar and browse and program buttons, the Config interface provides an
Initialize Chain button, console window, and status bar. The Initialize Chain button is useful if USB
communications with the board have been interrupted. The console window displays current status,
and the status bar shows real-time progress when downloading a configuration file.
Memory Interface
The Memory tab allows .bin, .bit, and .mcs
configuration files to be transferred to the on-
board BPI (parallel) or SPI (serial) PCM devices
for subsequent FPGA programming, and allows
user data files to be transferred to/from the
PCM devices or RAM memories at user-
specified addresses. The target memory is
selected by clicking one of the three radio
buttons in the upper-right corner.
Doc: 502-182
page 4 of 22
Nexys3 Reference Manual
The configuration tool supports programming
from any valid ROM file produced by the Xilinx
tools. After programming, board power can
either be cycled or the Reset button can be
pressed to program the FPGA from the PCM
device selected by the J8 mode jumper. If
programming with a .bit file, the startup clock
must be set to CCLK.
All three memory devices (the PCM's and the
cellular RAM) can be fully tested by clicking the
Full Test button. They can also be completely
erased by clicking the Erase button.
The Read/Write tools allow data to be
exchanged between files on the host PC and
specified address ranges in the memory
devices.
Test Interface
The test interface provides an easy way to
verify many of the board's hardware circuits and
interfaces. These are divided into two major
categories: on-board memory (RAM and Flash)
and peripherals. In both cases, the FPGA is
configured with test and PC-communication
circuits, overwriting any FPGA configuration
that may have been present.
Clicking the Run RAM/Flash Test button will
identify the CellularRam, SPI Flash, and BPI
Flash memory by reading out and verifying the
IDCODE on each memory. The memory
contents will not be modified. To run a full test
on a particular memory device, refer to the Full
Test in the Memory Tab.
Clicking the Start Peripherals Test button will
initialize GPIO and user I/O testing. Once the
indicator near the Start Peripherals Test button
turns green, all peripheral tests can be run.
The Test Shorts feature checks all discrete
I/O’s for shorts to Vdd, GND, and neighboring
I/O pins. The switches and buttons graphics
show the current states of those devices on the
Nexys3 board. Connect a VGA monitor and
USB mouse to visually test the J2 VGA port and
J4 USB port respectively.
Doc: 502-182
page 5 of 22
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时光少年
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2016-03-19 13:09:56
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