Verilog-A
Language Reference Manual
Analog Extensions to Verilog HDL
Version 1.0
August 1, 1996
Open Verilog International
No part of this work covered by the copyright hereon may be reproduced or used in any form or by any means --
- graphic, electronic, or mechanical, including photocopying, recording, taping, or information storage and
retrieval systems --- without the prior written approval of Open Verilog International.
Additional copies of this manual may be purchased by contacting Open Verilog International at the address
shown below.
Notices
The information contained in this draft manual represents the definition of the Verilog-A hardware description
language as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warran-
ties whatsoever with respect to the completeness, accuracy, or applicability of the information in this draft man-
ual to a user’s requirements. This language is not yet fully defined and is subject to change. It is suitable for
learning how to do analog modeling and as a vehicle for providing feedback to the standards committee. Verilog-
A should not be used for production design and development.
Open Verilog International reserves the right to make changes to the Verilog-A hardware description language
and this manual at any time without notice.
Open Verilog International does not endorse any particular simulator or other CAE tool that is based on the Ver-
ilog-A hardware description language.
Suggestions for improvements to the Verilog hardware description language and/or to this manual are welcome.
They should be sent to the address below.
Information about Open Verilog International and membership enrollment can be obtained by inquiring at the
address below.
Published as:
Verilog-A Language Reference Manual
Version 1.0, August 1, 1996.
Open Verilog International
15466 Los Gatos Blvd., #109071
Los Gatos, CA 95032
Phone: (408) 358-9510
Fax: (408) 358-3910
Published by:
Printed in the United States of America.
Verilog
®
is a registered trademark of Cadence Design Systems, Inc.
The following people contributed to the creation, editing and review of this document.
Ramana Aisola
Kevin Cameron
Dan FitzPatrick
Vassilios Gerousis
Ian Getreu
Kim Hailey
Ken Kundert
Oskar Leuthold
S. Peter Liebmann
Ira Miller
Tom Reeder
Steffen Rochel
James Spoto
Richard Trihy
Yatin Trivedi
Alex Zamfirescu
Motorola
Meta-Software
Apteq
Motorola
Analogy
Meta Software
Cadence
GEC Plessy
Meta Software
Motorola
Viewlogic
Anacad/Mentor
Cadence
Cadence
SEVA Technologies
Veribest
aisola@analog-dse.sps.mot.com
kevinc@metasw.com
dkf@apteq.com
gerousis@chdasic.sps.mot.com
iang@analogy.com
kimh@metasw.com
kundert@cadence.com
leuthold@sv.gpsemi.com
peterl@metasw.com
miller@analog-dse.sps.mot.com
treeder@viewlogic.com
steffen_rochel@mentorg.com
spoto@cadence.com
trihy@cadence.com
trivedi@seva.com
a.zamfirescu@ieee.org
Table of Contents
Verilog-A HDL Overview
Overview ........................................................................................... 1-1
Systems ............................................................................................. 1-1
Conservative systems .................................................................. 1-2
Kirchhoff’s laws .......................................................................... 1-3
Signal-flow systems .................................................................... 1-4
Mixed systems ............................................................................ 1-5
Natures, disciplines and nodes .................................................... 1-7
Conventions used in this document .................................................. 1-8
Contents ............................................................................................ 1-9
Lexical Tokens
Lexical tokens ................................................................................... 2-1
White space ....................................................................................... 2-1
Comments ......................................................................................... 2-1
Operators ........................................................................................... 2-2
Numbers ............................................................................................ 2-2
Integer constants ......................................................................... 2-2
Real constants ............................................................................. 2-3
Units for real constants ............................................................... 2-4
Conversion .................................................................................. 2-4
Identifiers, keywords, and system names ......................................... 2-5
Escaped identifiers ...................................................................... 2-5
Keywords .................................................................................... 2-5
Version 1.0
Verilog-A Language Reference Manual
v
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论