CY7C9335A
SMPTE-259M/DVB-ASI
Descrambler/Framer-Controller
Features
• Fully compatible with SMPTE-259M
• Fully compatible with DVB-ASI
• Operates from a single +5V supply
• 100-pin TQFP package
• Decodes 10-bit parallel digital streams for 27M
characters/sec (270 Mbits/sec serial)
• Operates with CY7B9334 SMPTE HOTLink
®
deseri-
alizer/receiver
• X
9
+ X
4
+ 1 descrambler and NRZI-to-NRZ decoder may
be bypassed for raw data output
The inputs of the CY7C9335A are designed to be directly
mated to a CY7B9334 HOTLink receiver, which converts the
SMPTE-259M compatible high-speed serial data stream into
10-bit parallel characters.
This device performs both TRS (sync) detection and framing,
data descrambling with the SMPTE-259M X
9
+X
4
+1 algorithm,
and NRZI-to-NRZ decoding. These functions operate at a 27
MHz character rate. For those systems operating with
non-SMPTE-259M compliant video streams (or for diagnostic
purposes), the descrambler and NRZI decoding functions can
be disabled.
DVB-ASI Operation
The CY7C9335A also contains the necessary multiplexers,
control inputs and outputs, to control a DVB-ASI-compliant
video stream. DVB-ASI operation is enabled through
activation of a single input signal. This allows a single
serial-to-parallel input port to support both SMPTE and DVB
data streams under software or hardware control.
In DVB-ASI mode the CY7C9335A automatically enables both
the 8B/10B decoder and multibyte framer present in the
CY7B9334 receiver/deserializer. All error detection, fill, and
command codes are detected and output by the CY7C9335A.
The CY7C9335A operates from a single +5V supply. It is
available in a 100-pin TQFP space saving package.
Functional Description
SMPTE-259M Operation
The CY7C9335A is a CMOS integrated circuit designed to
decode SMPTE-125M bit-parallel digital characters (or other
data formats) using the SMPTE-259M decoding rules.
Following decoding, the characters are framed by locating the
30-bit TRS pattern in the parallel character stream. The
framed characters are then output.
Logic Block Diagram
D
9
(RVS)
BARREL SHIFTER
RF
A/B
PD
9
(SVS)
PD
8
D
7
D
6
D
5
D
4
TRS DETECTOR/FRAMER
NRZI-TO-NRZ DECODER
SMPTE DESCRAMBLER
D
8
19
10
MODE MULTIPLEXOR
OUTPUT REGISTER
10
10
PD
7
PD
6
PD
5
PD
4
PD
3
PD
2
PD
1
PD (SC/D)
0
H_SYNC
SYNC_ERR
11
INPUT REGISTER
10
D
3
D
2
D
1
D
0
(SC/D)
4
SYNC_EN
BYPASS
DVB_EN
CKR
OE
OFFSET
Cypress Semiconductor Corporation
Document #: 38-02083 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised March 19, 2010
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CY7C9335A
Pin Configuration
TQFP
Top View
NC
V
CC
A/B
RF
NC
D
9
(RVS)
D
8
D
7
D
6
D
5
V
CC
V
SS
V
SS
V
CC
V
SS
D
4
D
3
D
2
D
1
D
0
(SC/D)
NC
NC
NC
V
SS
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
SS
V
SS
NC
NC
NC
NC
NC
NC
NC
OE
V
SS
V
CC
NC
V
SS
V
SS
BYPASS
NC
NC
SYNC_EN
NC
NC
DVB_EN
NC
V
CC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
SS
V
CC
NC
NC
NC
NC
NC
NC
NC
NC
CKR
V
SS
NC
V
CC
V
SS
NC
NC
SYNC_ERR
NC
H_SYNC
NC
NC
NC
V
SS
NC
Pin Descriptions
CY7C9335A SMPTE-259M Decoder
Name
BYPASS
I/O
Input
Description
Bypass SMPTE decoding.
BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at the
rising edge of CKR (and DVB_EN is HIGH), the data latched into the input register is routed around both
the NRZI decoder and the SMPTE descrambler and presented to the output register. If BYPASS is LOW
at the rising edge of the CKR clock (and DVB_EN is HIGH), the data present in the input register is routed
through the NRZI decoder and SMPTE scrambler.
Reframe.
This output is the inverted DVB-EN signal.
CY7B9334 Port Select.
When in DVB-ASI mode, this output will alternately select either the INA± or
INB± receiver port based on errors detected in the data stream. This allows CY7C9335A to operate with
normal and inverted DVB-ASI data streams (as would be commonly found on DVB-ASI streams routed
through SMPTE switches). This requires the CY7B9334 INA± and INB± inputs to be connected to the
same signal, but with INB± connected to invert the signal.
Horizontal Sync.
This output toggles once every time that the TRS field is recognized. It changes state
one clock cycle prior to the first character of the TRS field (3FF in 10-bit hex) appearing at the PD
0−9
outputs. This output also toggles to indicate detection of a TRS sequence, even when the TRS characters
are at a different offset from the present offset and SYNC_EN is active (HIGH). This toggling action is
disabled when DVB_EN is active (LOW).
RF
A/B
Output
Output
H_SYNC
Output
Document #: 38-02083 Rev. *A
NC
V
SS
NC
PD
9
(RVS)
NC
PD
8
PD
7
NC
PD
6
PD
5
V
SS
V
CC
NC
V
SS
V
CC
PD
4
PD
3
NC
PD
2
NC
PD
1
NC
PD (SC/D)
0
V
CC
NC
Page 2 of 8
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CY7C9335A
Pin Descriptions
CY7C9335A SMPTE-259M Decoder (continued)
Name
SYNC_EN
I/O
Input
Description
Sync Filtering Enabled.
This input controls the operation of the SMPTE framer. When this signal is
active (HIGH) and a TRS sequence is detected, if the 10-bit character boundary is different from the
previously received TRS, the H_SYNC output is toggled, but the character offset is not updated. If the
immediately following TRS also has a different offset, the H_SYNC output is again toggled and the
character offset is updated to match that of the detected TRS sequence. When this signal is inactive
(LOW), the framer will update the character offset and toggle H_SYNC on every detected TRS sequence.
Sync Error.
This output pulses HIGH for one CKR clock period when a TRS sequence is detected that
is offset from its previous 10-bit character offset. This pulse starts at the same time as the H_SYNC signal
toggles, but only occurs when SYNC_EN is active (HIGH) and the character offset is not updated.
Parallel Data 9 or Received Violation Symbol.
This is the MSB of the framed output data bus. It is
latched in the output register at the rising edge of CKR. When DVB_EN is active (LOW), this output
indicates that the character present on PD
8−0
identifies the type of error detected in the character stream.
When DVB_EN is disabled (HIGH), the character in the output register bits PD
9−0
is a descrambled and
framed character of the SMPTE data stream.
Parallel Data 8 through 1.
The signals present at the PD
8−1
outputs are latched in the output register
at the rising edge of CKR. When DVB_EN is disabled (HIGH), these signals are the middle eight bits of
the descrambled and framed SMPTE 10-bit data character. When DVB_EN is active (LOW), these
signals are full DVB-ASI data bus.
Parallel Data 0 or Special Code/Data Select.
This is the LSB of the output data field. It is latched in the
output register at the rising edge of CKR. When DVB_EN is active (LOW), this output identifies that the
character present in PD
8−1
is either a command (HIGH) or data (LOW) character). When DVB_EN is
inactive (HIGH), this output data bit is the LSB of the descrambled and framed SMPTE data character.
Input Bit 9.
This is the MSB of the input register. It should be connected directly to the CY7B9334
deserializer output signal RVS(Q
j
).
Input Bits 8 through 1.
These signals should be connected directly to the CY7B9334 deserializer output
signals Q
7−0
respectively.
Input Bit 0.
This is the LSB of the input register. It should be connected directly to the CY7B9334
deserializer output signal SC/D(Q
a
).
DVB Mode Enable.
This signal is sampled by the rising edge of the CKR clock. If DVB_EN is active
(LOW), the data present on the D
0−9
inputs are latched and routed to the PD
0−9
outputs.
Recovered Clock Read.
This clock controls all synchronous operations of the CY7C9335A. It operates
at the character rate which is equivalent to one tenth the deserialized bit-rate. This clock is driven directly
by the CKR output of the CY7B9334 deserializer.
Output Enable.
When this signal is HIGH all outputs are driven to their normal logic levels. When LOW,
all outputs are placed in a High-Z state.
Power.
Ground.
SYNC_ERR Output
PD
9
(RVS)
Output
PD
8−1
Output
PD
0
(SC/D)
Output
D
9
(RVS)
D
8−1
D
0
(SC/D)
DVB_EN
CKR
Input
Input
Input
Input
Input
OE
V
CC
V
SS
Input
Document #: 38-02083 Rev. *A
Page 3 of 8
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CY7C9335A
CY7C9335A Description
Input Register
The input register is clocked by the rising edge of CKR. This
register captures the data present at the D
0−9
inputs on every
clock cycle. In addition to the data inputs, all control inputs
except OE are also captured at each rising edge of CKR. This
includes BYPASS, DVB_EN, and SYNC_EN.
NRZI-to-NRZ Decoder
The data in the input register is routed through an
NRZI-to-NRZ decoder prior to being fed to the SMPTE
descrambler. This removes the extra transitions added to the
data stream by the NRZI encoder at the transmit end of the
interface.
SMPTE Descrambler
Once the data has been converted back to NRZ, it is then
routed through a linear feed-forward descrambler. It decodes
the data present in the NRZ decode register using the
X
9
+ X
4
+ 1 polynomial to remove the extra transitions added
to the data stream at the transmit end of the interface.
TRS Framer
The TRS Framer is used to detect all 30-bit TRS sequences
(3FF, 000, 000 in 10-bit hex) in the character stream. Anytime
this sequence is detected, the H_SYNC output toggles.
This sequence is also used to frame the received characters
so that the characters delivered to the output register are on
their correct 10-bit boundaries. If SYNC_EN is disabled (LOW)
and the TRS sequence is detected in the decoded data
stream, the character offset register is set to match the offset
of the TRS sequence, and both the TRS sequence and the
following characters are output on their proper 10-bit bound-
aries.
If SYNC_EN is enabled, and a TRS sequence is detected
whose character offset does not match that in the offset
register, an internal flag is set but the offset register is not
updated. On the next consecutive TRS sequence this flag is
cleared and the offset register is updated.
DVB-ASI Operation
The CY7C9335A is designed to operate in both SMPTE-259M
and DVB-ASI environments. When operated in SMPTE-only
environments, the DVB_EN inputs must be tied to V
CC
or
driven HIGH.
DVB-ASI operation is enabled by asserting DVB_EN LOW.
This signal is latched by the rising edge of the CKR clock.
When the CY7C9335A is placed in DVB mode, the SMPTE
and NRZI decoders are bypassed, and the data latched into
the input register is routed directly to the output register.
Error Detected
Errors detected in the DVB-ASI data stream are indicated by
the Q
9
bit being HIGH. The specific type of error is identified
by the remaining Q
8−0
bits in the output register.
Command Code Reception
The DVB-ASI interface does not normally transmit any
command characters other than the K28.5 code that is used
both for synchronization and as a fill character when data is
not being transmitted. These K28.5 characters are normally
received as C5.0 characters. If other command characters are
also transmitted, these characters are identified by Q
0
being
HIGH, and by the bits present on Q
8−1
.
DVB Invert Controller
DVB-ASI data streams are use 8B/10B encoded characters. If
these characters are routed through SMPTE switches or
repeaters, the signals may be inverted causing them to
decode into incorrect or illegal characters. The CY7C9335A
contains a state machine that, in conjunction with the
CY7B9334 SMPTE HOTLink receiver, allows inverted
DVB-ASI data streams to be decoded into their correct
characters.
This state machine is only enabled when in DVB mode. It
monitors the data stream for errors, and inverts the data
stream at the CY7B9334 if it exceeds a preset statistical error
rate. For this to operate the A/B output of the CY7C9335A
needs to be connected to the A/B input of the CY7B9334
SMPTE HOTLink receiver (through the appropriate resistive
divider).
If the CY7C9335A is not used for DVB-ASI operation, the A/B
output may be left open.
Document #: 38-02083 Rev. *A
Page 4 of 8
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CY7C9335A
Maximum Ratings
[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −40°C
to +125°C
Supply Voltage to Ground Potential
.................−0.5V
to +7.0V
DC Voltage Applied to Outputs
in High-Z State
.....................................................−0.5V
to +7.0V
Output Current Into Outputs.........................................16 mA
DC Input Voltage
................................................ −0.5V
to +7.0V
Static Discharge Voltage
..............................................>
2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current
..........................................................>
200 mA
Operating Range
Range
Commercial
Ambient Temperature
0°C to +70°C
V
CC
5V
±
5%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short Circuit
Current
[3,4]
Test Conditions
I
OH
=
−3.2
mA, V
CC
= Min.
I
OL
= 16.0 mA, V
CC
= Min
Note 2
Note 2
GND
≤
V
I
≤
V
CC
GND
≤
V
O
≤
V
CC
, Output Disabled
V
CC
= Max., V
OUT
= 0.5V
2.0
−0.5
−10
−50
−30
Min.
2.4
0.5
7.0
0.8
+10
+50
−160
Max.
Unit
V
V
V
V
μA
μA
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
C
CLK
Description
Input Capacitance
Output Capacitance
Clock Signal Capacitance
Test Conditions
f = 1 MHz, V
CC
= 5.0V
Max.
10
12
12
Unit
pF
pF
pF
AC Test Loads and Waveforms
238Ω
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
170Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
170Ω
GND
<2 ns
238Ω
5.0V
90%
10%
90%
10%
<2 ns
ALL INPUT PULSES
(a)
Equivalent to:
THÉVENIN EQUIVALENT
99Ω
OUTPUT
5 OR 35 pF
2.08V
(b)
(c)
Notes:
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. These are absolute values with respect to device ground. All overshoots with respect to system or tester noise are included.
3. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
OUT
= 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
4. Tested initially and after any design or process changes that may effect these parameters.
Document #: 38-02083 Rev. *A
Page 5 of 8
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