PCI Local Bus Specification
Revision 3.0
August 12, 2002
PCI SPECIFICATIONS
REVISION
1.0
2.0
2.1
2.2
2.3
3.0
Original issue
REVISION HISTORY
Incorporated connector and add-in card specification
Incorporated clarifications and added 66 MHz chapter
Incorporated ECNs and improved readability
Incorporated ECNs, errata, and deleted 5 volt only keyed
add-in cards
Removed support for the 5.0 volt keyed system board
connector
DATE
6/22/92
4/30/93
6/1/95
12/18/98
3/29/02
8/12/02
PCI-SIG disclaims all warranties and liability for the use of this document and the
information contained herein and assumes no responsibility for any errors that may appear
in this document, nor does PCI-SIG make a commitment to update the information
contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding this PCI specification or membership in PCI-SIG may be forwarded to:
PCI-SIG
5440 SW Westgate Drive
Suite 217
Portland, Oregon 97221
Phone: 800-433-5177 (Inside the U.S.)
503-291-2569 (Outside the U.S.)
Fax: 503-297-1090
e-mail administration@pcisig.com
http://www.pcisig.com
DISCLAIMER
This PCI Local Bus Specification is provided "as is" with no warranties whatsoever,
including any warranty of merchantability, noninfringement, fitness for any particular
purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of
information in this specification. No license, express or implied, by estoppel or otherwise,
to any intellectual property rights is granted herein.
All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
Copyright © 1992, 1993, 1995, 1998, 2002 PCI-SIG
VOLUME 1
PCI LOCAL BUS SPECIFICATION, REV. 3.0
2
PCI-SIG
PCI SPECIFICATIONS
Contents
PREFACE ......................................................................................................................... 13
S
PECIFICATION
S
UPERSEDES
E
ARLIER
D
OCUMENTS
...................................................... 13
I
NCORPORATION OF
E
NGINEERING
C
HANGE
N
OTICES
(ECN
S
)....................................... 13
D
OCUMENT
C
ONVENTIONS
............................................................................................ 14
1.
INTRODUCTION..................................................................................................... 15
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
2.
S
PECIFICATION
C
ONTENTS
................................................................................. 15
M
OTIVATION
...................................................................................................... 15
PCI L
OCAL
B
US
A
PPLICATIONS
......................................................................... 16
PCI L
OCAL
B
US
O
VERVIEW
............................................................................... 17
PCI L
OCAL
B
US
F
EATURES AND
B
ENEFITS
........................................................ 18
A
DMINISTRATION
............................................................................................... 20
SIGNAL DEFINITION............................................................................................. 21
2.1. S
IGNAL
T
YPE
D
EFINITION
.................................................................................. 22
2.2. P
IN
F
UNCTIONAL
G
ROUPS
.................................................................................. 22
2.2.1.
System Pins................................................................................................ 23
2.2.2.
Address and Data Pins.............................................................................. 24
2.2.3.
Interface Control Pins............................................................................... 25
2.2.4.
Arbitration Pins (Bus Masters Only) ........................................................ 27
2.2.5.
Error Reporting Pins................................................................................. 27
2.2.6.
Interrupt Pins (Optional) .......................................................................... 28
2.2.7.
Additional Signals ..................................................................................... 31
2.2.8.
64-Bit Bus Extension Pins (Optional) ....................................................... 33
2.2.9.
JTAG/Boundary Scan Pins (Optional)...................................................... 34
2.2.10. System Management Bus Interface Pins (Optional) ................................. 35
2.3. S
IDEBAND
S
IGNALS
............................................................................................ 36
2.4. C
ENTRAL
R
ESOURCE
F
UNCTIONS
....................................................................... 36
3.
BUS OPERATION ................................................................................................... 37
3.1. B
US
C
OMMANDS
................................................................................................ 37
3.1.1.
Command Definition ................................................................................. 37
3.1.2.
Command Usage Rules ............................................................................. 39
3.2. PCI P
ROTOCOL
F
UNDAMENTALS
....................................................................... 42
3.2.1.
Basic Transfer Control.............................................................................. 43
3.2.2.
Addressing................................................................................................. 44
3.2.3.
Byte Lane and Byte Enable Usage ............................................................ 56
3.2.4.
Bus Driving and Turnaround .................................................................... 57
3.2.5.
Transaction Ordering and Posting ........................................................... 58
3.2.6.
Combining, Merging, and Collapsing....................................................... 62
PCI-SIG
PCI LOCAL BUS SPECIFICATION, REV. 3.0
3
VOLUME 1
PCI SPECIFICATIONS
3.3. B
US
T
RANSACTIONS
........................................................................................... 64
3.3.1.
Read Transaction ...................................................................................... 65
3.3.2.
Write Transaction...................................................................................... 66
3.3.3.
Transaction Termination........................................................................... 67
3.4. A
RBITRATION
..................................................................................................... 87
3.4.1.
Arbitration Signaling Protocol.................................................................. 89
3.4.2.
Fast Back-to-Back Transactions ............................................................... 91
3.4.3.
Arbitration Parking................................................................................... 94
3.5. L
ATENCY
............................................................................................................ 95
3.5.1.
Target Latency........................................................................................... 95
3.5.2.
Master Data Latency................................................................................. 98
3.5.3.
Memory Write Maximum Completion Time Limit..................................... 99
3.5.4.
Arbitration Latency ................................................................................. 100
3.6. O
THER
B
US
O
PERATIONS
................................................................................. 110
3.6.1.
Device Selection ...................................................................................... 110
3.6.2.
Special Cycle ........................................................................................... 111
3.6.3.
IDSEL Stepping ....................................................................................... 113
3.6.4.
Interrupt Acknowledge ............................................................................ 114
3.7. E
RROR
F
UNCTIONS
........................................................................................... 115
3.7.1.
Parity Generation.................................................................................... 115
3.7.2.
Parity Checking....................................................................................... 116
3.7.3.
Address Parity Errors ............................................................................. 116
3.7.4.
Error Reporting....................................................................................... 117
3.7.5.
Delayed Transactions and Data Parity Errors ....................................... 120
3.7.6.
Error Recovery........................................................................................ 121
3.8. 64-B
IT
B
US
E
XTENSION
................................................................................... 123
3.8.1.
Determining Bus Width During System Initialization............................. 126
3.9. 64-
BIT
A
DDRESSING
......................................................................................... 127
3.10.
S
PECIAL
D
ESIGN
C
ONSIDERATIONS
.............................................................. 130
4.
ELECTRICAL SPECIFICATION.......................................................................... 137
4.1. O
VERVIEW
....................................................................................................... 137
4.1.1.
Transition Road Map .............................................................................. 137
4.1.2.
Dynamic vs. Static Drive Specification ................................................... 138
4.2. C
OMPONENT
S
PECIFICATION
............................................................................ 139
4.2.1.
5V Signaling Environment ...................................................................... 140
4.2.2.
3.3V Signaling Environment ................................................................... 146
4.2.3.
Timing Specification................................................................................ 150
4.2.4.
Indeterminate Inputs and Metastability .................................................. 155
4.2.5.
Vendor Provided Specification................................................................ 156
4.2.6.
Pinout Recommendation ......................................................................... 157
VOLUME 1
PCI LOCAL BUS SPECIFICATION, REV. 3.0
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PCI-SIG
PCI SPECIFICATIONS
4.3. S
YSTEM
B
OARD
S
PECIFICATION
....................................................................... 158
4.3.1.
Clock Skew .............................................................................................. 158
4.3.2.
Reset ........................................................................................................ 158
4.3.3.
Pull-ups ................................................................................................... 161
4.3.4.
Power ...................................................................................................... 163
4.3.5.
System Timing Budget ............................................................................. 164
4.3.6.
Physical Requirements ............................................................................ 167
4.3.7.
Connector Pin Assignments .................................................................... 168
4.4. A
DD
-
IN
C
ARD
S
PECIFICATION
.......................................................................... 171
4.4.1.
Add-in Card Pin Assignment................................................................... 171
4.4.2.
Power Requirements ............................................................................... 176
4.4.3.
Physical Requirements ............................................................................ 178
4.4.4.
Signal Loading ........................................................................................ 179
5.
MECHANICAL SPECIFICATION........................................................................ 181
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
6.
O
VERVIEW
....................................................................................................... 181
A
DD
-
IN
C
ARD
P
HYSICAL
D
IMENSIONS AND
T
OLERANCES
............................... 182
C
ONNECTOR
P
HYSICAL
D
ESCRIPTION
.............................................................. 195
C
ONNECTOR
P
HYSICAL
R
EQUIREMENTS
.......................................................... 205
C
ONNECTOR
P
ERFORMANCE
S
PECIFICATION
.................................................... 206
S
YSTEM
B
OARD
I
MPLEMENTATION
.................................................................. 207
CONFIGURATION SPACE .................................................................................. 213
6.1. C
ONFIGURATION
S
PACE
O
RGANIZATION
.......................................................... 213
6.2. C
ONFIGURATION
S
PACE
F
UNCTIONS
................................................................ 216
6.2.1.
Device Identification ............................................................................... 216
6.2.2.
Device Control ........................................................................................ 217
6.2.3.
Device Status ........................................................................................... 219
6.2.4.
Miscellaneous Registers.......................................................................... 221
6.2.5.
Base Addresses........................................................................................ 224
6.3. PCI E
XPANSION
ROM
S
................................................................................... 228
6.3.1.
PCI Expansion ROM Contents................................................................ 229
6.3.2.
Power-on Self Test (POST) Code............................................................ 232
6.3.3.
PC-compatible Expansion ROMs ........................................................... 232
6.4. V
ITAL
P
RODUCT
D
ATA
..................................................................................... 235
6.5. D
EVICE
D
RIVERS
.............................................................................................. 236
6.6. S
YSTEM
R
ESET
................................................................................................. 236
6.7. C
APABILITIES
L
IST
........................................................................................... 237
6.8. M
ESSAGE
S
IGNALED
I
NTERRUPTS
.................................................................... 237
6.8.1.
MSI Capability Structure ........................................................................ 238
6.8.2.
MSI-X Capability & Table Structures..................................................... 244
6.8.3.
MSI and MSI-X Operation ...................................................................... 248
PCI-SIG
PCI LOCAL BUS SPECIFICATION, REV. 3.0
5
VOLUME 1
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