MSP430FR58xx, MSP430FR59xx,
MSP430FR68xx, and MSP430FR69xx Family
User's Guide
Literature Number: SLAU367F
October 2012 – Revised January 2015
Contents
Preface
.......................................................................................................................................
35
1
System Resets, Interrupts, and Operating Modes, System Control Module (SYS)
.......................
37
1.1
1.2
1.3
System Control Module (SYS) Introduction
............................................................................
System Reset and Initialization
...........................................................................................
1.2.1 Device Initial Conditions After System Reset
..................................................................
Interrupts
....................................................................................................................
1.3.1 (Non)Maskable Interrupts (NMIs)
...............................................................................
1.3.2 SNMI Timing
.......................................................................................................
1.3.3 Maskable Interrupts
...............................................................................................
1.3.4 Interrupt Processing
...............................................................................................
1.3.5 Interrupt Nesting
...................................................................................................
1.3.6 Interrupt Vectors
...................................................................................................
1.3.7 SYS Interrupt Vector Generators
................................................................................
Operating Modes
...........................................................................................................
1.4.1 Low-Power Modes and Clock Requests
.......................................................................
1.4.2 Entering and Exiting Low-Power Modes LPM0 Through LPM4
.............................................
1.4.3 Low Power Modes LPM3.5 and LPM4.5 (LPMx.5)
...........................................................
Principles for Low-Power Applications
..................................................................................
Connection of Unused Pins
...............................................................................................
Reset Pin (RST/NMI) Configuration
.....................................................................................
Configuring JTAG Pins
....................................................................................................
Vacant Memory Space
....................................................................................................
Boot Code
...................................................................................................................
1.10.1 IP Encapsulation (IPE) Instantiation by Boot Code
..........................................................
1.10.2 IP Encapsulation Signatures
...................................................................................
1.10.3 IP Encapsulation Init Structure
.................................................................................
1.10.4 IP Encapsulation Removal
.....................................................................................
Bootstrap Loader (BSL)
...................................................................................................
JTAG Mailbox (JMB) System
............................................................................................
1.12.1 JMB Configuration
...............................................................................................
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox
.................................................................
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox
.......................................................................
1.12.4 JMB NMI Usage
..................................................................................................
JTAG and SBW Lock Mechanism Using the Electronic Fuse
........................................................
1.13.1 JTAG and SBW Lock Without Password
.....................................................................
1.13.2 JTAG and SBW Lock With Password
.........................................................................
Device Descriptor Table
...................................................................................................
1.14.1 Identifying Device Type
..........................................................................................
1.14.2 TLV Descriptors
..................................................................................................
1.14.3 Calibration Values
................................................................................................
SFR Registers
..............................................................................................................
1.15.1 SFRIE1 Register
.................................................................................................
1.15.2 SFRIFG1 Register
...............................................................................................
1.15.3 SFRRPCR Register
..............................................................................................
SYS Registers
..............................................................................................................
38
38
40
40
41
41
41
42
43
43
44
46
48
49
49
51
52
52
52
53
53
53
53
54
54
55
55
55
56
56
56
56
57
57
57
58
59
60
63
64
65
67
68
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
2
Contents
SLAU367F – October 2012 – Revised January 2015
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
www.ti.com
1.16.1
1.16.2
1.16.3
1.16.4
1.16.5
1.16.6
1.16.7
1.16.8
1.16.9
SYSCTL Register
................................................................................................
SYSJMBC Register
..............................................................................................
SYSJMBI0 Register
..............................................................................................
SYSJMBI1 Register
..............................................................................................
SYSJMBO0 Register
............................................................................................
SYSJMBO1 Register
............................................................................................
SYSUNIV Register
...............................................................................................
SYSSNIV Register
...............................................................................................
SYSRSTIV Register
.............................................................................................
69
70
71
71
72
72
73
73
74
76
77
77
77
78
78
78
79
79
79
80
81
82
83
84
2
Power Management Module (PMM) and Supply Voltage Supervisor (SVS)
.................................
75
2.1
2.2
Power Management Module (PMM) Introduction
......................................................................
PMM Operation
.............................................................................................................
2.2.1 V
CORE
and the Regulator
..........................................................................................
2.2.2 Supply Voltage Supervisor
.......................................................................................
2.2.3 Supply Voltage Supervisor - Power-Up
........................................................................
2.2.4 LPM3.5 and LPM4.5
..............................................................................................
2.2.5 Brownout Reset (BOR)
...........................................................................................
2.2.6 RST/NMI
............................................................................................................
2.2.7 PMM Interrupts
....................................................................................................
2.2.8 Port I/O Control
....................................................................................................
PMM Registers
.............................................................................................................
2.3.1 PMMCTL0 Register (offset = 00h) [reset = 9640h]
...........................................................
2.3.2 PMMCTL1 Register (offset = 02h) [reset = 9600h]
...........................................................
2.3.3 PMMIFG Register (offset = 0Ah) [reset = 0000h]
.............................................................
2.3.4 PM5CTL0 Register (offset = 10h) [reset = 0001h]
............................................................
2.3
3
Clock System (CS) Module
..................................................................................................
85
3.1
3.2
Clock System Introduction
................................................................................................
86
Clock System Operation
...................................................................................................
88
3.2.1 CS Module Features for Low-Power Applications
............................................................
88
3.2.2 LFXT Oscillator
....................................................................................................
88
3.2.3 HFXT Oscillator
....................................................................................................
89
3.2.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
..................................................
90
3.2.5 Module Oscillator (MODOSC)
...................................................................................
90
3.2.6 Digitally Controlled Oscillator (DCO)
............................................................................
90
3.2.7 Operation From Low-Power Modes, Requested by Peripheral Modules
..................................
91
3.2.8 CS Module Fail-Safe Operation
.................................................................................
92
3.2.9 Synchronization of Clock Signals
...............................................................................
94
Module Oscillator (MODOSC)
............................................................................................
94
3.3.1 MODOSC Operation
..............................................................................................
94
CS Registers
................................................................................................................
95
3.4.1 CSCTL0 Register
..................................................................................................
96
3.4.2 CSCTL1 Register
..................................................................................................
96
3.4.3 CSCTL2 Register
..................................................................................................
97
3.4.4 CSCTL3 Register
..................................................................................................
98
3.4.5 CSCTL4 Register
..................................................................................................
99
3.4.6 CSCTL5 Register
................................................................................................
101
3.4.7 CSCTL6 Register
................................................................................................
102
MSP430X CPU (CPUX) Introduction
...................................................................................
Interrupts
...................................................................................................................
CPU Registers
............................................................................................................
4.3.1 Program Counter (PC)
..........................................................................................
4.3.2 Stack Pointer (SP)
...............................................................................................
Contents
3.3
3.4
4
CPUX
..............................................................................................................................
103
4.1
4.2
4.3
104
106
107
107
107
3
SLAU367F – October 2012 – Revised January 2015
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
www.ti.com
4.4
4.5
4.6
4.3.3 Status Register (SR)
............................................................................................
4.3.4 Constant Generator Registers (CG1 and CG2)
.............................................................
4.3.5 General-Purpose Registers (R4 to R15)
......................................................................
Addressing Modes
........................................................................................................
4.4.1 Register Mode
....................................................................................................
4.4.2 Indexed Mode
....................................................................................................
4.4.3 Symbolic Mode
...................................................................................................
4.4.4 Absolute Mode
...................................................................................................
4.4.5 Indirect Register Mode
..........................................................................................
4.4.6 Indirect Autoincrement Mode
...................................................................................
4.4.7 Immediate Mode
.................................................................................................
MSP430 and MSP430X Instructions
...................................................................................
4.5.1 MSP430 Instructions
............................................................................................
4.5.2 MSP430X Extended Instructions
..............................................................................
Instruction Set Description
...............................................................................................
4.6.1 Extended Instruction Binary Descriptions
.....................................................................
4.6.2 MSP430 Instructions
............................................................................................
4.6.3 Extended Instructions
...........................................................................................
4.6.4 Address Instructions
.............................................................................................
32-Bit Hardware Multiplier (MPY32) Introduction
.....................................................................
MPY32 Operation
.........................................................................................................
5.2.1 Operand Registers
...............................................................................................
5.2.2 Result Registers
.................................................................................................
5.2.3 Software Examples
..............................................................................................
5.2.4 Fractional Numbers
..............................................................................................
5.2.5 Putting It All Together
...........................................................................................
5.2.6 Indirect Addressing of Result Registers
......................................................................
5.2.7 Using Interrupts
..................................................................................................
5.2.8 Using DMA
........................................................................................................
MPY32 Registers
.........................................................................................................
5.3.1 MPY32CTL0 Register
...........................................................................................
FRAM Introduction
........................................................................................................
FRAM Organization
.......................................................................................................
FRCTL Module Operation
...............................................................................................
Programming FRAM Memory Devices
.................................................................................
6.4.1 Programming FRAM Memory Via JTAG or Spy-Bi-Wire
...................................................
6.4.2 Programming FRAM Memory Via Bootstrap Loader (BSL)
................................................
6.4.3 Programming FRAM Memory Via Custom Solution
.........................................................
Wait State Control
........................................................................................................
6.5.1 Wait State and Cache Hit
.......................................................................................
FRAM ECC
................................................................................................................
FRAM Write Back
........................................................................................................
FRAM Power Control
.....................................................................................................
FRAM Cache
..............................................................................................................
FRCTL Registers
.........................................................................................................
6.10.1 FRCTL0 Register
...............................................................................................
6.10.2 GCCTL0 Register
...............................................................................................
6.10.3 GCCTL1 Register
...............................................................................................
Memory Protection Unit (MPU) Introduction
109
110
111
113
114
115
119
124
126
127
128
130
130
135
147
148
150
202
245
261
263
264
265
266
267
270
273
273
274
275
277
279
279
279
280
280
280
280
280
281
281
281
281
282
283
284
285
286
288
5
32-Bit Hardware Multiplier (MPY32)
.....................................................................................
260
5.1
5.2
5.3
6
FRAM Controller (FRCTL)
..................................................................................................
278
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
Memory Protection Unit (MPU)
...........................................................................................
287
7.1
..........................................................................
4
Contents
SLAU367F – October 2012 – Revised January 2015
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
www.ti.com
7.2
7.3
7.4
7.5
7.6
MPU Segments
...........................................................................................................
7.2.1 Main Memory Segments
........................................................................................
7.2.2 IP Encapsulation Segment
.....................................................................................
7.2.3 Segment Border Setting
........................................................................................
7.2.4 IP Encapsulation Border Settings
..............................................................................
7.2.5 Information Memory
.............................................................................................
MPU Access Management Settings
....................................................................................
MPU Violations
............................................................................................................
7.4.1 Interrupt Vector Table and Reset Vector
.....................................................................
7.4.2 Violation Handling
...............................................................................................
MPU Lock
..................................................................................................................
MPU Registers
............................................................................................................
7.6.1 MPUCTL0 Register
..............................................................................................
7.6.2 MPUCTL1 Register
..............................................................................................
7.6.3 MPUSEGB2 Register
...........................................................................................
7.6.4 MPUSEGB1 Register
...........................................................................................
7.6.5 MPUSAM Register
...............................................................................................
7.6.6 MPUIPC0 Register
..............................................................................................
7.6.7 MPUIPSEGB2 Register
.........................................................................................
7.6.8 MPUIPSEGB1 Register
.........................................................................................
RAM Controller (RAMCTL) Introduction
...............................................................................
RAMCTL Operation
.......................................................................................................
8.2.1 Considerations for Complete Power Down
...................................................................
RAMCTL Registers
.......................................................................................................
8.3.1 RCCTL0 Register (offset = 00h) [reset = 6900h]
............................................................
Direct Memory Access (DMA) Introduction
............................................................................
DMA Operation
............................................................................................................
9.2.1 DMA Addressing Modes
........................................................................................
9.2.2 DMA Transfer Modes
............................................................................................
9.2.3 Initiating DMA Transfers
........................................................................................
9.2.4 Halting Executing Instructions for DMA Transfers
...........................................................
9.2.5 Stopping DMA Transfers
........................................................................................
9.2.6 DMA Channel Priorities
.........................................................................................
9.2.7 DMA Transfer Cycle Time
......................................................................................
9.2.8 Using DMA With System Interrupts
...........................................................................
9.2.9 DMA Controller Interrupts
.......................................................................................
9.2.10 Using the eUSCI_B I
2
C Module With the DMA Controller
.................................................
9.2.11 Using ADC12 With the DMA Controller
......................................................................
DMA Registers
............................................................................................................
9.3.1 DMACTL0 Register
..............................................................................................
9.3.2 DMACTL1 Register
..............................................................................................
9.3.3 DMACTL2 Register
..............................................................................................
9.3.4 DMACTL3 Register
..............................................................................................
9.3.5 DMACTL4 Register
..............................................................................................
9.3.6 DMAxCTL Register
..............................................................................................
9.3.7 DMAxSA Register
...............................................................................................
9.3.8 DMAxDA Register
...............................................................................................
9.3.9 DMAxSZ Register
................................................................................................
9.3.10 DMAIV Register
.................................................................................................
Digital I/O Introduction
289
289
290
291
292
293
293
294
294
294
294
295
296
297
298
299
300
302
303
304
306
306
306
307
308
310
312
312
313
319
320
320
320
321
321
321
322
323
324
326
327
328
329
330
331
333
334
335
336
338
5
8
RAM Controller (RAMCTL)
.................................................................................................
305
8.1
8.2
8.3
9
DMA Controller
.................................................................................................................
309
9.1
9.2
9.3
10
Digital I/O
.........................................................................................................................
337
10.1
...................................................................................................
Contents
Copyright © 2012–2015, Texas Instruments Incorporated
SLAU367F – October 2012 – Revised January 2015
Submit Documentation Feedback
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论