USB 2.0 4-Port Hub
Data Sheet Rev. 1.01
FE1.1
S
USB 2.0 H
IGH
S
PEED
4-P
ORT
H
UB
C
ONTROLLER
_______________________Data Sheet_______________________
I
NTRODUCTION
The FE1.1s is a highly integrated, high quality,
high performance, low power consumption, yet
low cost solution for USB 2.0 High Speed 4-Port
Hub.
It adopts
Single Transaction Translator
(STT)
architecture to be more cost effective. Six,
instead of two, non-periodic transaction buffers
are used to minimize potential traffic jamming.
The whole design is based on state-machine-
control to reduce the response delay time; no
micro controller is used in this chip.
To guarantee high quality, the whole chip is
covered by
Test Scan Chain
– even on the high
speed (480MHz) modules, so that all the logic
components could be fully tested before shipping.
Special
Build-In-Self-Test
mode is designed to
exercise all high, full, and low speed Analog
Front End (AFE) components on the packaging
and testing stages as well.
Low power consumption is achieved by using
0.18μm technology and comprehensive
power/clock control mechanism. Most part of the
chip will not be clocked unless needed.
F
EATURES
Fully compliant with Universal Serial Bus
Specification Revision 2.0 (USB 2.0);
□
Upstream facing port supports High-
Speed (480MHz) and Full-Speed
(12MHz) modes;
□
4 downstream facing ports support
High-Speed (480MHz), Full-Speed
(12MHz), and Low-Speed (1.5MHz)
modes;
Integrated USB 2.0 Transceivers;
Integrated upstream 1.5KΩ pull-up,
downstream 15KΩ pull-down, and serial
resisters;
Integrated 5V to 3.3V and 1.8V regulator.
Integrated Power-On-Reset circuit;
Integrated 12MHz Oscillator with feedback
resister, and crystal load capacitance;
Integrated 12MHz-to-480MHz Phase Lock
Loop (PLL);
Single Transaction Translator
(STT) –
□
One TT for all downstream ports;
□
The TT could handle 64 periodic Start-
Split transactions, 32 periodic
Complete-Split transactions, and 6
none-periodic transactions;
Automatic self-power status monitoring;
□
Automatic re-enumeration when Self-
1
Feb. 9, 2009
Subject to Change Without Notice
USB 2.0 4-Port Hub
Data Sheet Rev. 1.01
Powered switching to Bus-Powered;
Ganged Power Control
and
Global Over-
Current Detection
support;
EEPROM configured options –
□
Vendor ID, Product ID,
&
Device
Release Number;
and
□
Number of Downstream Ports;
Comprehensive Port Indicators support:
□
Downstream Port Enabled
indicator
LED (x4, Green);
□
Hub Active/Suspend
indicator LED.
Feb. 9, 2009
Subject to Change Without Notice
2
USB 2.0 4-Port Hub
Data Sheet Rev. 1.01
B
LOCK
D
IAGRAM
To Downstream
Devices
To Upstream
Host/Hub
Down-
stream
PHY #1
Down-
stream
PHY #2
Down-
stream
PHY #3
Down-
stream
PHY #4
Upstream
PHY
Routing Switch
USB Multi-port Transceiver Macro Cell
12M Hz
Crystal
3.3V & 1.8V Regulator
OSC
Over Current
Detection
Power Switch
Control
POR
PLL
(x40)
Data
Transmit
Data
Recovery &
Elastic
Buffer
Upstream
Port
Controller
Downstream
Port
Controllers
USB 2.0
Hub
Controlle
r
SIE
Transaction Translator
Full/Low-Speed Handler
Transaction Translator
High-Speed Handler
Hub Controller
EEPROM,
Hub Activity
LED
Port
Indicators
Unified Transaction
Translator Buffer (2KB)
LED
Controller
Fig. 1: Block Diagram
Feb. 9, 2009
Subject to Change Without Notice
3
USB 2.0 4-Port Hub
Data Sheet Rev. 1.01
P
ACKAGE
28-pin SSOP
(Body Size: 10x4 mm, Pitch: 0.64 mm)
P
IN
A
SSIGNMENT
VSS
XOUT
XIN
DM4
DP4
DM3
DP3
DM2
DP2
DM1
DP1
VD18_O
VD33
REXT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VD18
TESTJ
OVCJ
PWRJ
LED2
LED1
DRV
VD33_O
VDD5
BUSJ
VBUSM
XRSTJ
DPU
DMU
FE1.1s
22
21
20
19
18
17
16
15
Fig. 2: SSOP-28 Pin Assignment
Feb. 9, 2009
Subject to Change Without Notice
4
USB 2.0 4-Port Hub
Data Sheet Rev. 1.01
P
IN
D
ESCRIPTION
T
ABLE
Pin Name Pin No. Type
VSS
XOUT
XIN
DM4
DP4
DM3
DP3
DM2
DP2
DM1
DP1
VD18_O
VD33
REXT
DMU
DPU
XRSTJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
25
16
17
UT
UT
I
P
Ground.
Function
Note
OSC 12 MHz Crystal Oscillator output
OSC 12 MHz Crystal Oscillator input.
UT
UT
UT
UT
UT
UT
UT
UT
P
P
The D- pin of the 4
th
Downstream Facing Port.
The D+ pin of the 4
th
Downstream Facing Port.
The D- pin of the 3
rd
Downstream Facing Port.
The D+ pin of the 3
rd
Downstream Facing Port.
The D- pin of the 2
nd
Downstream Facing Port.
The D+ pin of the 2
nd
Downstream Facing Port.
The D- pin of the 1
st
Downstream Facing Port.
The D+ pin of the 1
st
Downstream Facing Port.
1.8V power output from 3.3V→1.8V integrated regulator – a 10μF
decoupling capacitor is required.
3.3V power input for 3.3V→1.8V integrated regulator.
A 2.7KΩ (± 1%) resister should be connected to VSS to provide internal
bias reference.
The D- pin of the Upstream Facing Port.
The D+ pin of the Upstream Facing Port.
External Reset, active low, is an optional source of chip reset signal,
beside the build-in Power-On-Reset. The minimum low pulse width is 10
μs.
VBUSM
BUSJ
VDD5
VD33_O
TEST
DRV
LED1/
EESCL
LED2
18
19
20
21
―—
22
23
24
I
I
P
P
I
I/O
I/O
I/O
The V
BUS
Monitor of upstream facing port.
Bus power indicator:
0 – Bus Powered;
1 – Self Powered.
5V power input for integrated 5V→3.3V regulator.
3.3V power output from 5V→3.3V integrated regulator – a 10μF
decoupling capacitor is required.
Test Mode Enable – should be tied to ground for normal operation.
LED Drive Control
Port 1 and Port 3 Enabled Indicator (LED) Control, and external Serial
EEPROM Clock.
Port 2 and Port 4 Enabled Indicator (LED) Control
1
1
1
Feb. 9, 2009
Subject to Change Without Notice
5
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论