ARMv8 Instruction Set Overview
ARMv8 Instruction Set Overview
Architecture Group
Document number:
Date of Issue:
PRD03-GENC-010197 15.0
11 November 2011
© Copyright ARM Limited 2009-2011. All rights reserved.
Abstract
This document provides a high-level overview of the ARMv8 instructions sets, being mainly the new A64
instruction set used in AArch64 state but also those new instructions added to the A32 and T32 instruction sets
since ARMv7-A for use in AArch32 state. For A64 this document specifies the preferred architectural assembly
language notation to represent the new instruction set.
Keywords
AArch64, A64, AArch32, A32, T32, ARMv8
PRD03-GENC-010197
Copyright © 2009-2011 ARM Limited. All rights reserved.
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ARMv8 Instruction Set Overview
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PRD03-GENC-010197
Copyright © 2009-2011 ARM Limited. All rights reserved.
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ARMv8 Instruction Set Overview
Contents
1
ABOUT THIS DOCUMENT
Change control
Current status and anticipated changes
Change history
References
Terms and abbreviations
INTRODUCTION
A64 OVERVIEW
Distinguishing 32-bit and 64-bit Instructions
Conditional Instructions
Addressing Features
Register Indexed Addressing
PC-relative Addressing
The Program Counter (PC)
Memory Load-Store
Bulk Transfers
Exclusive Accesses
Load-Acquire, Store-Release
Integer Multiply/Divide
Floating Point
Advanced SIMD
A64 ASSEMBLY LANGUAGE
Basic Structure
Instruction Mnemonics
Condition Codes
Register Names
General purpose (integer) registers
FP/SIMD registers
Load/Store Addressing Modes
A64 INSTRUCTION SET
Copyright © 2009-2011 ARM Limited. All rights reserved.
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1.1
1.1.1
1.1.2
1.2
1.3
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3
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.7
3.8
4
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.5
5
PRD03-GENC-010197
ARMv8 Instruction Set Overview
5.1
5.1.1
5.1.2
5.1.3
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.5
5.5.1
5.5.2
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
5.6.10
5.6.11
5.7
5.7.1
5.7.2
5.7.3
Control Flow
Conditional Branch
Unconditional Branch (immediate)
Unconditional Branch (register)
Memory Access
Load-Store Single Register
Load-Store Single Register (unscaled offset)
Load Single Register (pc-relative, literal load)
Load-Store Pair
Load-Store Non-temporal Pair
Load-Store Unprivileged
Load-Store Exclusive
Load-Acquire / Store-Release
Prefetch Memory
Data Processing (immediate)
Arithmetic (immediate)
Logical (immediate)
Move (wide immediate)
Address Generation
Bitfield Operations
Extract (immediate)
Shift (immediate)
Sign/Zero Extend
Data Processing (register)
Arithmetic (shifted register)
Arithmetic (extending register)
Logical (shifted register)
Variable Shift
Bit Operations
Conditional Data Processing
Conditional Comparison
Integer Multiply / Divide
Multiply
Divide
Scalar Floating-point
Floating-point/SIMD Scalar Memory Access
Floating-point Move (register)
Floating-point Move (immediate)
Floating-point Convert
Floating-point Round to Integral
Floating-point Arithmetic (1 source)
Floating-point Arithmetic (2 source)
Floating-point Min/Max
Floating-point Multiply-Add
Floating-point Comparison
Floating-point Conditional Select
Advanced SIMD
Overview
Advanced SIMD Mnemonics
Data Movement
Copyright © 2009-2011 ARM Limited. All rights reserved.
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PRD03-GENC-010197
ARMv8 Instruction Set Overview
5.7.4
5.7.5
5.7.6
5.7.7
5.7.8
5.7.9
5.7.10
5.7.11
5.7.12
5.7.13
5.7.14
5.7.15
5.7.16
5.7.17
5.7.18
5.7.19
5.7.20
5.7.21
5.7.22
5.7.23
5.7.24
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
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6.1
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.2
6.4.3
6.5
6.6
6.6.1
6.6.2
Vector Arithmetic
Scalar Arithmetic
Vector Widening/Narrowing Arithmetic
Scalar Widening/Narrowing Arithmetic
Vector Unary Arithmetic
Scalar Unary Arithmetic
Vector-by-element Arithmetic
Scalar-by-element Arithmetic
Vector Permute
Vector Immediate
Vector Shift (immediate)
Scalar Shift (immediate)
Vector Floating Point / Integer Convert
Scalar Floating Point / Integer Convert
Vector Reduce (across lanes)
Vector Pairwise Arithmetic
Scalar Reduce (pairwise)
Vector Table Lookup
Vector Load-Store Structure
AArch32 Equivalent Advanced SIMD Mnemonics
Crypto Extension
System Instructions
Exception Generation and Return
System Register Access
System Management
Architectural Hints
Barriers and CLREX
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A32 & T32 INSTRUCTION SETS
Partial Deprecation of
IT
Load-Acquire / Store-Release
Non-Exclusive
Exclusive
VFP Scalar Floating-point
Floating-point Conditional Select
Floating-point minNum/maxNum
Floating-point Convert (floating-point to integer)
Floating-point Convert (half-precision to/from double-precision)
Floating-point Round to Integral
Advanced SIMD Floating-Point
Floating-point minNum/maxNum
Floating-point Convert
Floating-point Round to Integral
Crypto Extension
System Instructions
Halting Debug
Barriers and Hints
PRD03-GENC-010197
Copyright © 2009-2011 ARM Limited. All rights reserved.
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