英文论文
A key problem that arises in System-on-a-Chip (SOC) designs
of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS
is done by merging all the clock trees belonging to different
IPs per chip specifications. A primary requirement of CCTS
is to balance the sub-clock-trees belonging to different IPs such
that the entire tree has a small skew across all process corners.
This helps in timing closure across all the design corners.
Another important requirement of CCTS is to reduce
clock divergence between IPs that have critical timing paths
between them, thereby reducing maximum possible clock skew
in the critical paths and thus improves yield. In this work,
we propose effective CCTS algorithms to simultaneously reduce
multi-corner skew and clock divergence. To the best of
our knowledge, this is the first work that attempts to solve this
practically important problem. Experimental results on several
testcases indicate that our methods achieve 10%-31%(20% on
average) clock divergence reduction and between 16-64ps skew
reduction (1.6%-6.4% of cycle time for a 1GHz clock) with less
than 0.5% increase in buffer area/wirelength compared
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