Hardware Data Sheet
ET1100
Slave Controller
Section I – Technology
(Online at
http://www.beckhoff.com)
Section II – Register Description
(Online at
http://www.beckhoff.com)
Section III – Hardware Description
Pinout, Interface description, electrical
and mechanical specification, ET1100
features and registers
Version 1.9
Date:
2014-07-07
DOCUMENT ORGANIZATION
DOCUMENT ORGANIZATION
The Beckhoff EtherCAT Slave Controller (ESC) documentation covers the following Beckhoff ESCs:
ET1200
ET1100
EtherCAT IP Core for Altera
®
FPGAs
EtherCAT IP Core for Xilinx
®
FPGAs
ESC20
The documentation is organized in three sections. Section I and section II are common for all Beckhoff
ESCs, Section III is specific for each ESC variant.
The latest documentation is available at the Beckhoff homepage (http://www.beckhoff.com).
Section I – Technology (All ESCs)
Section I deals with the basic EtherCAT technology. Starting with the EtherCAT protocol itself, the
frame processing inside EtherCAT slaves is described. The features and interfaces of the physical
layer with its two alternatives Ethernet and EBUS are explained afterwards. Finally, the details of the
functional units of an ESC like FMMU, SyncManager, Distributed Clocks, Slave Information Interface,
Interrupts, Watchdogs, and so on, are described.
Since Section I is common for all Beckhoff ESCs, it might describe features which are not available in
a specific ESC. Refer to the feature details overview in Section III of a specific ESC to find out which
features are available.
Section II – Register Description (All ESCs)
Section II contains detailed information about all ESC registers. This section is also common for all
Beckhoff ESCs, thus registers, register bits, or features are described which might not be available in
a specific ESC. Refer to the register overview and to the feature details overview in Section III of a
specific ESC to find out which registers and features are available.
Section III – Hardware Description (Specific ESC)
Section III is ESC specific and contains detailed information about the ESC features, implemented
registers, configuration, interfaces, pinout, usage, electrical and mechanical specification, and so on.
Especially the Process Data Interfaces (PDI) supported by the ESC are part of this section.
Additional Documentation
Application notes and utilities like pinout configuration tools for ET1100 can also be found at the
Beckhoff homepage.
Trademarks
Beckhoff
®
, TwinCAT
®
, EtherCAT
®
, Safety over EtherCAT
®
, TwinSAFE
®
and XFC
®
are registered trademarks of and licensed by
Beckhoff Automation GmbH. Other designations used in this publication may be trademarks whose use by third parties for their
own purposes could violate the rights of the owners.
Patent Pending
The EtherCAT Technology is covered, including but not limited to the following German patent applications and patents:
DE10304637, DE102004044764, DE102005009224, DE102007017835 with corresponding applications or registrations in
various other countries.
Disclaimer
The documentation has been prepared with care. The products described are, however, constantly under development. For that
reason the documentation is not in every case checked for consistency with performance data, standards or other
characteristics. In the event that it contains technical or editorial errors, we retain the right to make alterations at any time and
without warning. No claims for the modification of products that have already been supplied may be made on the basis of the
data, diagrams and descriptions in this documentation.
Copyright
© Beckhoff Automation GmbH 07/2014.
The reproduction, distribution and utilization of this document as well as the communication of its contents to others without
express authorization are prohibited. Offenders will be held liable for the payment of damages. All rights reserved in the event of
the grant of a patent, utility model or design.
III-II
Slave Controller – ET1100 Hardware Description
DOCUMENT HISTORY
DOCUMENT HISTORY
Version
0.6
0.7
Comment
Editorial Changes
Synchronous µController Interface LSB/MSB clarification table added
EEPROM_LOADED pull-down recommendation added
Chip label updated
VCC
I/O
/GND
I/O
pins adjacent to LDO indicated
Frame processing order example corrected
I
2
C EEPROM interface description added
MII management interface description added
Corrected Process RAM size in Register Overview
P_CONF does not correspond with physical ports. See new port configuration
tables for details.
Revision/Build information added
CLK25OUT1/2 availability completed
Recommendations for unused input pins added (should not be left open)
EEPROM_SIZE description corrected from Kbyte to Kbit, possible EEPROM
sizes range from 16 Kbit to 4 Mbit
RoHS compliance added
Autonegotiation is mandatory for ESCs
Description of power supply options added
Electrical characteristics added/revised
SPI_IRQ delay added, support for SPI masters with 2 or 4 bytes added
TX Shift timing diagram and description added
Internal 27 kΩ PU/PD resistors at EBUS-RX pins added
LED polarity depending on configuration pin setting described
Recommendation for voltage stabilization capacitors added
Description of Digital I/O behavior on watchdog expiration enhanced
8 bit asynchronous µController PDI connection added
EBUS ports are open failsafe
Reset example schematic added
Ethernet PHY requirements and PHY connection schematic added
MI_DATA pull-up requirement added
µController PDI: DATA bus signal direction corrected
Pin/Signal description overview added
PERR(x) LEDs are only for testing/debugging
Editorial changes
RUN, LINKACT/x) and PERR(x) LED activity level corrected: active high if pulled
down, active low if pulled up
DC Characteristics enhanced: added V
Reset Core
, V
ID
, V
IC
Synchronous µController interface: timing characteristics enhanced
Note on RBIAS if no EBUS ports/only MII ports are used
DC SYNC/LATCH signal description and timing characteristics added
MII Interface chapter and MII timing characteristics added
EBUS Interface chapter added
Frame processing order, PHY requirements, EEPROM Interface description and
MII Management Interface description moved to Section I
TX Shift description moved to MII Interface chapter
Ambient temperature range instead of junction temperature range
Editorial changes
0.8
1.0
Slave Controller – ET1100 Hardware Description
III-III
DOCUMENT HISTORY
Version
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Comment
Port configurations with 2 ports: P_CONF[3] erroneously named P_MODE[3]
Clarified I/O voltage with respect to I/O power supply (only 3.3V I/O with
V
CCI/O
=3.3V, and no 5V input tolerance unless V
CCI/O
=5V)
Update to ET1100 stepping 1
Added/revised OSC_IN, CLK25OUT1/2, and MII TX signal timings
Added soldering profile
PHY address configuration changed
Added feature detail overview, removed redundant feature details
PDI and DC SYNC/LATCH signals are not driven until EEPROM is loaded
Synchronous 8/16 bit µController interface: clarified that clock is CPU_CLK_IN
Editorial changes
PHY address configuration chapter added, configuration revised
Enhanced link detection for MII available depending on PHY address
configuration
Ethernet Management Interface: read and write times were interchanged
Reserved pins are input pins
Editorial changes
Added reset timing figure and power-on value sample time
Distributed Clocks SYNC/LATCH signals are configurable and unidirectional
Information on CLK25OUT/CPU_CLK clock output during reset added
Description of internal PU/PD resistors at EBUS_RX pins enhanced
Added t
Diff
timing characteristic
Power supply example schematic clarified
Enhanced package information: MSL, ball’s material, and solder joint
recommendation
Digital I/O PDI: added SOF/OUTVALID description, dispensable timings
removed
Editorial changes
Register 0x0980 is only available if DC Sync Unit is enabled (0x0140.10=1)
Updated solder joint recommendation
OSC_IN/OSC_OUT pin capacitance added, crystal connection note extended
Release Notes added
Timing requirement for asynchronous µController PDI (t
ADR_BHE_setup
) relaxed
Input threshold voltage for OSC_IN added
Example schematic for transparent mode added
Renamed Err(x) LED to PERR(x)
Digital I/O PDI: OE_CONF functionality in bidirectional mode corrected
Digital I/O PDI: output event description corrected (EOF mode and WD_TRIG
mode)
SPI PDI: access error if SPI_DI not 1 in the last read byte (not SPI_DO)
Async./sync. µC PDI: access error with A(0)=1 and nBHE=1 (not nBHE=0),
timing requirements and diagrams clarified
Async. µC PDI: timing requirement for asynchronous µController PDI
(t
ADR_BHE_setup
) relaxed
AC timing: forwarding delay figures enhanced
Editorial changes
Reset timing figure corrected
Maximum soldering profile added
SPI PDI updated
SII EEPROM interface is a point-to-point connection
Editorial changes
Update to ET1100-0002
Editorial changes
µC PDI timing updated
Editorial changes
III-IV
Slave Controller – ET1100 Hardware Description
DOCUMENT HISTORY
Version
1.8
1.9
Comment
Enhanced Link Detection must not be activated if EBUS ports are used
Enhanced Link Detection for MII ports requires PHY address offset = 0
Digital Output principle schematic updated
Chip label updated
Editorial changes
Update to ET1100-0003
Enhanced Link Detection for MII ports supports PHY address offset 0 and 16
Enhanced Link Detection for MII ports can be disabled at any time
Enhanced Link Detection for EBUS ports is always disabled
MII management interface issues additional MCLK cycle after write accesses
Remote link down signalling time configurable 0x0100[22]
Editorial changes
Slave Controller – ET1100 Hardware Description
III-V
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