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MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1), MSP430FR682x(1)
Mixed‑Signal Microcontrollers
‑
1 Device Overview
1.1
1
Features
– True Random Number Seed for Random
Number Generation Algorithm
– Lockable Memory Segments for IP
Encapsulation and Secure Storage
Multifunction Input/Output Ports
– All I/O Pins Support Capacitive Touch Capability
Without Need for External Components
– Accessible Bit-, Byte- and Word-Wise (in Pairs)
– Edge-Selectable Wakeup From LPM on Ports
P1, P2, P3, and P4
– Programmable Pullup and Pulldown on All Ports
Enhanced Serial Communication
– eUSCI_A0 and eUSCI_A1 Support:
• UART With Automatic Baud-Rate Detection
• IrDA Encode and Decode
• SPI at Rates up to 10 Mbps
– eUSCI_B0 and eUSCI_B1 Support:
• I
2
C With Multiple-Slave Addressing
• SPI at Rates up to 10 Mbps
Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable
Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
Development Tools and Software
– Free Professional Development Environments
With
EnergyTrace++™
Technology for Power
Profiling and Debugging
– Microcontroller Development Boards Available
Family Members
–
Section 3
Summarizes the Available Variants
and Packages
For Complete Module Descriptions, See the
MSP430FR58xx, MSP430FR59xx,
MSP430FR68xx, and MSP430FR69xx Family
User's Guide
(SLAU367)
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16-MHz Clock
– Wide Supply Voltage Range (1.8 V to 3.6 V)
(1)
• Optimized Ultra-Low-Power Modes
– Active Mode: Approximately 100 µA/MHz
– Standby (LPM3 With VLO): 0.4 µA (Typical)
– Real-Time Clock (RTC) (LPM3.5):
0.35 µA (Typical)
(2)
– Shutdown (LPM4.5): 0.04 µA (Typical)
• Ultra-Low-Power Ferroelectric RAM (FRAM)
– Up to 64KB of Nonvolatile Memory
– Ultra-Low-Power Writes
– Fast Write at 125 ns per Word (64KB in 4 ms)
– Unified Memory = Program + Data + Storage in
One Single Space
– 10
15
Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– Three-Channel Internal Direct Memory Access
(DMA)
– RTC With Calendar and Alarm Functions
– Five 16-Bit Timers With up to Seven
Capture/Compare Registers
– 16-Bit and 32-Bit Cyclic Redundancy Checker
(CRC16, CRC32)
• High-Performance Analog
– Up to 8-Channel Analog Comparator
– 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference and Sample-and-Hold and
up to 8 External Input Channels
– Integrated 116-Segment LCD Driver With
Contrast Control
• Code Security and Encryption
– 128-Bit or 256-Bit AES Security Encryption and
Decryption Coprocessor (MSP430FR69xx(1)
Only)
(1)
(2)
Minimum supply voltage is restricted by SVS levels.
The RTC is clocked by a 3.7-pF crystal.
•
•
•
•
•
•
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
1.2
•
•
•
Applications
•
•
•
Portable Medical Equipment
Sensor Management
Weigh Scales
Heat Cost Allocators
Utility Meters – Electricity, Water, and Gas
Thermostats
1.3
Description
This ultra-low-power MSP430FRxx FRAM microcontroller family consists of several devices featuring
embedded nonvolatile FRAM, a 16-bit CPU, and different sets of peripherals targeted for various
applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are
optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new
nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash, all at lower total power consumption.
Device Information
(1)
PART NUMBER
MSP430FR6972IPMR
MSP430FR6972IRGC
MSP430FR6922IG56
(1)
(2)
PACKAGE
LQFP (64)
VQFN (64)
TSSOP (56)
BODY SIZE
(2)
10 mm × 10 mm
9 mm × 9 mm
6.1 mm × 14 mm
For the most current part, package, and ordering information for all available devices, see the
Package
Option Addendum
in
Section 9,
or see the TI website at
www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data
in
Section 9.
2
Device Overview
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
1.4
Functional Block Diagram
Figure 1-1
shows the functional block diagram.
P1.x,P2.x P3.x,P4.x P5.x,P6.x
up to
up to
up to
2x8
2x8
2x8
P7.x
up to
1x8
P9.x
up to
1x8
PJ.x
up to
1x8
LFXIN/
HFXIN
LFXOUT/
HFXOUT
Capacitive Touch IO 0, Capacitive Touch IO 1
Comp_E
MCLK
Clock
System
ACLK
(up to 16
inputs)
ADC12_B
(up to 16
std. inputs,
up to 8
diff. inputs)
REF_A
Voltage
Reference
I/O Ports
P1, P2
2x8 I/Os
I/O Ports
P3, P4
2x8 I/Os
I/O Port
P5, P6
2x8 I/Os
I/O Port
P7
1x8 I/Os
PD
1x8 I/Os
I/O Port
P9
1x8 I/Os
PE
1x8 I/Os
I/O Port
PJ
1x8 I/Os
SMCLK
DMA
Controller
3 Channel
Bus
Control
Logic
MAB
CPUXV2
incl. 16
Registers
MDB
MAB
MDB
PC
PB
PA
1x16 I/Os 1x16 I/Os 1x16 I/Os
MPU
IP Encap
FRAM
CRC16
RAM
2KB
Tiny RAM
26B
Power
Mgmt
LDO
SVS
Brownout
TA2
AES256
Security
En-/De-
cryption
(128/256)
TA 3
Timer_A
5 CC
Registers
CRC-16-
CCITT
MPY32
EEM
(S: 3+1)
64KB
32KB
CRC32
CRC-32-
ISO-3309
Watch-
dog
Timer_A
2 CC
Registers
(int. only)
MDB
JTAG
Interface
MAB
Spy-Bi-
Wire
RTC_C
Calendar
RTC_ A
and
Counter
Mode
TB0
Timer_B
7 CC
Registers
(int./ext.)
TA0
Timer_A
3 CC
Registers
(int./ext.)
TA1
Timer_A
3 CC
Registers
(int./ext.)
eUSCI_A0
eUSCI_A1
(UART,
IrDA,
SPI)
eUSCI_B0
eUSCI_B1
(I2C,
SPI)
LCD_C
(up to
RTC_ A
116 seg;
static,
2 to 4 mux)
LPM3.5 Domain
NOTE: AES256 is not implemented in the MSP430FR682x, MSP430FR687x, MSP430FR682x1, and MSP430FR687x1
devices.
NOTE: HFXIN and HFOUT are not implemented in the MSP430FR692x, MSP430FR682x, MSP430FR692x1, and
MSP430FR682x1 devices.
Figure 1-1. Functional Block Diagram
Copyright © 2015, Texas Instruments Incorporated
Device Overview
3
Submit Documentation Feedback
Product Folder Links:
MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
SLASE23C – JANUARY 2015 – REVISED MAY 2015
www.ti.com
Table of Contents
1
Device Overview
.........................................
1
1.1
1.2
1.3
1.4
Features
..............................................
1
Applications
...........................................
2
Description
............................................
2
Functional Block Diagram
............................
3
5.13
Timing and Switching Characteristics
...............
35
6
Detailed Description
...................................
64
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
2
3
4
Revision History
.........................................
5
Device Comparison
.....................................
6
Terminal Configuration and Functions
..............
8
4.1
4.2
4.3
4.4
Pin Diagrams
.........................................
8
Pin Attributes
........................................
11
Signal Descriptions
..................................
17
Pin Multiplexing
25
25
............................................
CPU
.................................................
Operating Modes
....................................
Interrupt Vector Table and Signatures
..............
Bootstrap Loader (BSL)
.............................
JTAG Operation
.....................................
FRAM
................................................
RAM
.................................................
Tiny RAM
............................................
Overview
Peripherals
64
64
65
67
70
70
71
71
71
5
.....................................
4.5
Connection of Unused Pins
.........................
Specifications
...........................................
5.1
Absolute Maximum Ratings
.........................
5.2
ESD Ratings
........................................
5.3
Recommended Operating Conditions
...............
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
Active Mode Supply Current Into V
CC
Excluding
External Current
....................................
Typical Characteristics - Active Mode Supply
Currents
.............................................
Low-Power Mode (LPM0, LPM1) Supply Currents
Into V
CC
Excluding External Current
................
Low-Power Mode LPM2, LPM3, LPM4 Supply
Currents (Into V
CC
) Excluding External Current
....
Low-Power Mode With LCD Supply Currents (Into
V
CC
) Excluding External Current
....................
Low-Power Mode LPMx.5 Supply Currents (Into
V
CC
) Excluding External Current
....................
Typical Characteristics, Low-Power Mode Supply
Currents
.............................................
Typical Characteristics, Current Consumption per
Module
..............................................
Thermal Characteristics
Memory Protection Unit (MPU) Including IP
Encapsulation
.......................................
71
26
26
26
26
7
27
28
..........................................
72
6.12 Device Descriptors (TLV)
..........................
109
6.13 Memory
............................................
112
6.14 Identification
........................................
128
Applications, Implementation, and Layout
......
129
7.1
Device Connection and Layout Fundamentals
....
129
7.2
Peripheral- and Interface-Specific Design
Information
.........................................
133
Device Support
.....................................
136
Documentation Support
............................
139
8
28
29
31
32
33
34
34
Device and Documentation Support
..............
136
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
......................................
Community Resources
.............................
Trademarks
........................................
Electrostatic Discharge Caution
...................
Export Control Notice
..............................
Glossary
............................................
Related Links
139
140
141
141
141
141
9
............................
Mechanical, Packaging, and Orderable
Information
.............................................
141
9.1
Packaging Information
.............................
141
4
Table of Contents
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872
MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221
MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820
www.ti.com
SLASE23C – JANUARY 2015 – REVISED MAY 2015
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from April 28, 2015 to May 1, 2015
•
Page
Removed 48KB FRAM option from
Figure 1-1,
Functional Block Diagram
...................................................
3
Copyright © 2015, Texas Instruments Incorporated
Revision History
5
Submit Documentation Feedback
Product Folder Links:
MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721
MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221
MSP430FR6820
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