Berkeley
Phase Locked Loops (PLL) and Frequency
Synthesis
Prof. Ali M. Niknejad
U.C. Berkeley
Copyright
c
2014 by Ali M. Niknejad
Niknejad
PLLs and Frequency Synthesis
Phase Locked Loop Block Diagram
Loop Filter
Ref
Div
PD
VCO
÷N
Phase Locked Loops (PLL) are ubiquitous circuits used in
countless communication and engineering applications.
Components include a VCO, a frequency divider, a phase
detector (PD), and a loop filter.
Niknejad
PLLs and Frequency Synthesis
Phase Locked Loops
A PLL is a truly mixed-signal circuit, involving the co-design
of RF, digital, and analog building blocks.
A non-linear negative feedback loop that locks the
phase
of a
VCO to a reference signal.
Applications include generating a clean, tunable, and stable
reference (LO) frequency, a process referred to as
frequency
synthesis
Other applications: Frequency modulation and demodulation
(a natural “FM” modulator/demodulator). Clock recovery for
high speed communication, and the generation of phase
synchronous clock signals in microprocessors.
Electronic PLLs are common, but optical and mechanical also
used.
Niknejad
PLLs and Frequency Synthesis
Frequency Synthesizer
In a frequency synthesizer, the VCO is usually realized using
an
LC
tank (best phase noise), or alternatively a ring
oscillator (higher phase noise, smaller area).
The reference is derived from a precision XTAL oscillator. The
divider brings down the high frequency of the VCO signal to
the range of the reference frequency. The PD compares the
phase and produces an error signal, which is smoothed out by
the loop filter and applied to the VCO.
When the system locks, the output phase of the VCO is
locked to the XTAL. That means that the frequency is also
locked. The output frequency
f
out
is therefore an integer
multiple of the reference
f
ref
f
ref
=
f
out
/N
f
out
=
N
×
f
ref
Niknejad
PLLs and Frequency Synthesis
Programmable Divider
By making the divider
N
programmable, we can tune the
VCO frequency in either integer steps of the reference
(integer-N architecture) or in fractional amounts (fractional-N
architecture).
∆f = (N +
p)f
ref
−
Nf
ref
=
pf
ref
In a fractional divider,
p
<
1 and is realized by dithering the
divider between
N
and
N
+ 1 using a sigma-delta modulator.
In practice, the programmable divider is made of up
asynchronous high-speed dividers followed by programmable
CMOS dividers (counters).
The high speed dividers are sometimes in CML, which runs
faster than CMOS, and has superior noise immunity and
generation due to the differential nature. Injection locked or
TSPC dividers are also useful for very low power high
frequency operation.
Niknejad
PLLs and Frequency Synthesis
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