Intel
®
5 Series Chipset and Intel
®
3400 Series Chipset
Datasheet
June 2010
Document Number: 322169-003
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Datasheet
Contents
1
Introduction
............................................................................................................ 39
1.1
About This Manual ............................................................................................. 39
1.2
Overview ......................................................................................................... 42
1.2.1 Capability Overview ................................................................................ 44
1.3
Intel
®
5 Series Chipset and Intel
®
3400 Series Chipset SKU Definition ..................... 50
1.4
Reference Documents ........................................................................................ 52
Signal Description
................................................................................................... 53
2.1
Direct Media Interface (DMI) to Host Controller ..................................................... 55
2.2
PCI Express* .................................................................................................... 55
2.3
Firmware Hub Interface...................................................................................... 56
2.4
PCI Interface .................................................................................................... 57
2.5
Serial ATA Interface........................................................................................... 59
2.6
LPC Interface.................................................................................................... 62
2.7
Interrupt Interface ............................................................................................ 62
2.8
USB Interface ................................................................................................... 63
2.9
Power Management Interface.............................................................................. 65
2.10 Processor Interface............................................................................................ 68
2.11 SMBus Interface................................................................................................ 68
2.12 System Management Interface............................................................................ 68
2.13 Real Time Clock Interface ................................................................................... 69
2.14 Miscellaneous Signals ........................................................................................ 70
2.15 Intel
®
High Definition Audio Link ......................................................................... 71
2.16 Controller Link (Mobile Only)............................................................................... 72
2.17 Serial Peripheral Interface (SPI) .......................................................................... 72
2.18 Intel
®
Quiet System Technology and Thermal Reporting ......................................... 73
2.19 JTAG Signals .................................................................................................... 74
2.20 Clock Signals .................................................................................................... 74
2.21 LVDS Signals (Mobile only) ................................................................................. 76
2.22 Analog Display /CRT DAC Signals ........................................................................ 77
2.23 Intel
®
Flexible Display Interface (FDI).................................................................. 78
2.24 Digital Display Signals........................................................................................ 79
2.25 General Purpose I/O Signals ............................................................................... 82
2.26 Manageability Signals ........................................................................................ 85
2.27 Power and Ground Signals .................................................................................. 86
2.28 Pin Straps ........................................................................................................ 88
2.28.1 Functional Straps ................................................................................... 88
2.28.2 External RTC Circuitry ............................................................................. 92
PCH Pin States.........................................................................................................
93
3.1
Integrated Pull-Ups and Pull-Downs ..................................................................... 93
3.2
Output and I/O Signals Planes and States............................................................. 95
3.3
Power Planes for Input Signals .......................................................................... 106
System Clocks
....................................................................................................... 113
Functional Description
........................................................................................... 117
5.1
DMI-to-PCI Bridge (D30:F0) ............................................................................. 117
5.1.1 PCI Bus Interface ................................................................................. 117
5.1.2 PCI Bridge As an Initiator ...................................................................... 117
5.1.2.1 Memory Reads and Writes........................................................ 118
5.1.2.2 I/O Reads and Writes .............................................................. 118
5.1.2.3 Configuration Reads and Writes ................................................ 118
5.1.2.4 Locked Cycles ........................................................................ 118
5.1.2.5 Target / Master Aborts............................................................. 118
5.1.2.6 Secondary Master Latency Timer............................................... 118
5.1.2.7 Dual Address Cycle (DAC) ........................................................ 118
5.1.2.8 Memory and I/O Decode to PCI................................................. 119
5.1.3 Parity Error Detection and Generation ..................................................... 119
5.1.4 PCIRST# ............................................................................................. 120
5.1.5 Peer Cycles ......................................................................................... 120
5.1.6 PCI-to-PCI Bridge Model........................................................................ 121
5.1.7 IDSEL to Device Number Mapping .......................................................... 121
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Datasheet
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5.2
5.3
5.4
5.5
5.6
5.7
5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 121
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 121
5.2.1 Interrupt Generation ............................................................................. 122
5.2.2 Power Management............................................................................... 122
5.2.2.1 S3/S4/S5 Support ................................................................... 122
5.2.2.2 Resuming from Suspended State ............................................... 123
5.2.2.3 Device Initiated PM_PME Message ............................................. 123
5.2.2.4 SMI/SCI Generation................................................................. 123
5.2.3 SERR# Generation ................................................................................ 124
5.2.4 Hot-Plug .............................................................................................. 124
5.2.4.1 Presence Detection .................................................................. 124
5.2.4.2 Message Generation ................................................................ 125
5.2.4.3 Attention Button Detection ....................................................... 125
5.2.4.4 SMI/SCI Generation................................................................. 126
Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 126
5.3.1 GbE PCI Express* Bus Interface.............................................................. 128
5.3.1.1 Transaction Layer.................................................................... 128
5.3.1.2 Data Alignment ....................................................................... 128
5.3.1.3 Configuration Request Retry Status ........................................... 128
5.3.2 Error Events and Error Reporting ............................................................ 129
5.3.2.1 Data Parity Error ..................................................................... 129
5.3.2.2 Completion with Unsuccessful Completion Status ......................... 129
5.3.3 Ethernet Interface ................................................................................ 129
5.3.3.1 Intel
®
5 Series Chipset and Intel
®
3400 Series Chipset
82577/82578 PHY Interface...................................................... 129
5.3.4 PCI Power Management ......................................................................... 130
5.3.4.1 Wake Up ................................................................................ 130
5.3.5 Configurable LEDs................................................................................. 131
5.3.6 Function Level Reset Support (FLR) ......................................................... 132
5.3.6.1 FLR Steps............................................................................... 132
LPC Bridge (with System and Management Functions) (D31:F0)............................. 133
5.4.1 LPC Interface ....................................................................................... 133
5.4.1.1 LPC Cycle Types ...................................................................... 134
5.4.1.2 Start Field Definition ................................................................ 134
5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 135
5.4.1.4 Size....................................................................................... 135
5.4.1.5 SYNC..................................................................................... 136
5.4.1.6 SYNC Time-Out ....................................................................... 136
5.4.1.7 SYNC Error Indication .............................................................. 136
5.4.1.8 LFRAME# Usage...................................................................... 136
5.4.1.9 I/O Cycles .............................................................................. 137
5.4.1.10 Bus Master Cycles ................................................................... 137
5.4.1.11 LPC Power Management ........................................................... 137
5.4.1.12 Configuration and PCH Implications ........................................... 137
DMA Operation (D31:F0) .................................................................................. 138
5.5.1 Channel Priority.................................................................................... 138
5.5.1.1 Fixed Priority .......................................................................... 138
5.5.1.2 Rotating Priority ...................................................................... 139
5.5.2 Address Compatibility Mode ................................................................... 139
5.5.3 Summary of DMA Transfer Sizes ............................................................. 139
5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words 139
5.5.4 Autoinitialize ........................................................................................ 140
5.5.5 Software Commands ............................................................................. 140
LPC DMA ........................................................................................................ 141
5.6.1 Asserting DMA Requests ........................................................................ 141
5.6.2 Abandoning DMA Requests..................................................................... 142
5.6.3 General Flow of DMA Transfers ............................................................... 142
5.6.4 Terminal Count..................................................................................... 142
5.6.5 Verify Mode ......................................................................................... 143
5.6.6 DMA Request De-assertion ..................................................................... 143
5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 144
8254 Timers (D31:F0) ...................................................................................... 144
5.7.1 Timer Programming .............................................................................. 145
5.7.2 Reading from the Interval Timer ............................................................. 146
5.7.2.1 Simple Read ........................................................................... 146
5.7.2.2 Counter Latch Command .......................................................... 146
5.7.2.3 Read Back Command ............................................................... 146
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Datasheet
5.8
5.9
5.10
5.11
5.12
5.13
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 147
5.8.1 Interrupt Handling................................................................................ 148
5.8.1.1 Generating Interrupts.............................................................. 148
5.8.1.2 Acknowledging Interrupts ........................................................ 148
5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 149
5.8.2 Initialization Command Words (ICWx) ..................................................... 149
5.8.2.1 ICW1 .................................................................................... 149
5.8.2.2 ICW2 .................................................................................... 150
5.8.2.3 ICW3 .................................................................................... 150
5.8.2.4 ICW4 .................................................................................... 150
5.8.3 Operation Command Words (OCW) ......................................................... 150
5.8.4 Modes of Operation .............................................................................. 150
5.8.4.1 Fully Nested Mode................................................................... 150
5.8.4.2 Special Fully-Nested Mode........................................................ 151
5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 151
5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 151
5.8.4.5 Poll Mode............................................................................... 151
5.8.4.6 Cascade Mode ........................................................................ 152
5.8.4.7 Edge and Level Triggered Mode ................................................ 152
5.8.4.8 End of Interrupt (EOI) Operations ............................................. 152
5.8.4.9 Normal End of Interrupt........................................................... 152
5.8.4.10 Automatic End of Interrupt Mode .............................................. 152
5.8.5 Masking Interrupts ............................................................................... 153
5.8.5.1 Masking on an Individual Interrupt Request................................ 153
5.8.5.2 Special Mask Mode.................................................................. 153
5.8.6 Steering PCI Interrupts ......................................................................... 153
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 154
5.9.1 Interrupt Handling................................................................................ 154
5.9.2 Interrupt Mapping ................................................................................ 154
5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 155
5.9.4 IOxAPIC Address Remapping ................................................................. 155
5.9.5 External Interrupt Controller Support ...................................................... 155
Serial Interrupt (D31:F0) ................................................................................. 156
5.10.1 Start Frame......................................................................................... 156
5.10.2 Data Frames........................................................................................ 157
5.10.3 Stop Frame ......................................................................................... 157
5.10.4 Specific Interrupts Not Supported Using SERIRQ ...................................... 157
5.10.5 Data Frame Format .............................................................................. 158
Real Time Clock (D31:F0)................................................................................. 159
5.11.1 Update Cycles...................................................................................... 159
5.11.2 Interrupts ........................................................................................... 160
5.11.3 Lockable RAM Ranges ........................................................................... 160
5.11.4 Century Rollover .................................................................................. 160
5.11.5 Clearing Battery-Backed RTC RAM .......................................................... 160
Processor Interface (D31:F0) ............................................................................ 162
5.12.1 Processor Interface Signals and VLW Messages ........................................ 162
5.12.1.1 A20M# (Mask A20) / A20GATE ................................................. 162
5.12.1.2 INIT (Initialization) ................................................................. 163
5.12.1.3 FERR# (Numeric Coprocessor Error) .......................................... 163
5.12.1.4 NMI (Non-Maskable Interrupt) .................................................. 164
5.12.1.5 Processor Power Good (PROCPWRGD) ....................................... 164
5.12.2 Dual-Processor Issues........................................................................... 164
5.12.2.1 Usage Differences ................................................................... 164
5.12.3 Virtual Legacy Wire (VLW) Messages....................................................... 164
Power Management (D31:F0) ........................................................................... 165
5.13.1 Features ............................................................................................. 165
5.13.2 PCH and System Power States ............................................................... 165
5.13.3 System Power Planes ............................................................................ 167
5.13.4 SMI#/SCI Generation ........................................................................... 167
5.13.4.1 PCI Express* SCI.................................................................... 170
5.13.4.2 PCI Express* Hot-Plug............................................................. 170
5.13.5 C-States ............................................................................................. 170
5.13.6 Dynamic PCI Clock Control (Mobile Only)................................................. 170
5.13.6.1 Conditions for Checking the PCI Clock........................................ 171
5.13.6.2 Conditions for Maintaining the PCI Clock .................................... 171
5.13.6.3 Conditions for Stopping the PCI Clock ........................................ 171
5.13.6.4 Conditions for Re-Starting the PCI Clock .................................... 171
Datasheet
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