热搜关键词: 电路基础ADC数字信号处理封装库PLC

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AD9826数据手册

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标签: AD9826

AD9826

这是一款基础CDS的16bit  AD,能应用于CCD相机

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a FEATURES 16Bit 15 MSPS AD Converter 3Channel 16Bit Operation up to 15 MSPS 1Channel 16Bit Operation up to 125 MSPS 2Channel Mode for Mono Sensors with OddEven Outputs Correlated Double Sampling 16 Programmable Gain 300 mV Programmable Offset Input Clamp Circuitry Internal Voltage Reference Multiplexed ByteWide Output Optional Single Byte Output Mode 3Wire Serial Digital Interface 3 V5 V Digital IO Compatibility 28Lead SSOP Package Low Power CMOS 400 mW Typ PowerDown Mode Available APPLICATIONS......

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FEATURES
16-Bit 15 MSPS A/D Converter
3-Channel 16-Bit Operation up to 15 MSPS
1-Channel 16-Bit Operation up to 12.5 MSPS
2-Channel Mode for Mono Sensors with Odd/Even Outputs
Correlated Double Sampling
CDS
1~6 Programmable Gain
300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output
Optional Single Byte Output Mode
3-Wire Serial Digital Interface
3 V/5 V Digital I/O Compatibility
28-Lead SSOP Package
Low Power CMOS: 400 mW (Typ)
Power-Down Mode Available
APPLICATIONS
Flatbed Document Scanners
Digital Copier
Multifunction Peripherals
Infrared Imaging Applications
Machine Vision
Complete 16-Bit Imaging
Signal Processor
AD9826
PRODUCT DESCRIPTION
The AD9826 is a complete analog signal processor for imaging
applications. It features a 3-channel architecture designed to
sample and condition the outputs of trilinear color CCD arrays.
Each channel consists of an input clamp, Correlated Double
Sampler (CDS), offset DAC, and Programmable Gain Amplifier
(PGA), multiplexed to a high-performance 16-bit A/D converter.
The AD9826 can operate at speeds greater than 15 MSPS with
reduced performance.
CIS为接触式图像传感器
The CDS amplifiers may be disabled for use with sensors that
do not require CDS, such as Contact Image Sensors (CIS),
CMOS active pixel sensors, and Focal Plane Arrays.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single byte output mode. The internal registers are programmed
through a 3-wire serial interface, and provide adjustment of
the gain, offset, and operating mode.
The AD9826 operates from a single 5 V power supply, typically
consumes 400 mW of power, and is packaged in a 28-lead SSOP.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
CML
CAPT CAPB
AVDD
AVSS
DRVDD
DRVSS
VINR
CDS
9-BIT
DAC
PGA
BANDGAP
REFERENCE
AD9826
OEB
VING
CDS
9-BIT
DAC
PGA
3:1
MUX
16-BIT
ADC
16
16:8
MUX
8
DOUT
CONFIGURATION
REGISTER
PGA
MUX
REGISTER
6
RED
GREEN
BLUE
DIGITAL
CONTROL
INTERFACE
SCLK
SLOAD
SDATA
VINB
CDS
9-BIT
DAC
OFFSET
INPUT
CLAMP
BIAS
9
RED
GREEN
BLUE
GAIN
REGISTERS
OFFSET
REGISTERS
ADCCLK
CDSCLK1 CDSCLK2
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax:
© Analog Devices, Inc.,
AD9826–SPECIFICATIONS
ANALOG SPECIFICATIONS
Parameter
MAXIMUM CONVERSION RATE
3-Channel Mode with CDS
2-Channel Mode with CDS
1-Channel Mode with CDS
ACCURACY (ENTIRE SIGNAL PATH)
ADC Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
ANALOG INPUTS
Input Signal Range (Programmable)
1
Allowable Reset Transient
1
Input Limits
2
Input Capacitance
Input Bias Current
AMPLIFIERS
PGA Gain
PGA Gain Resolution
2
PGA Gain Monotonicity
Programmable Offset
Programmable Offset Resolution
Programmable Offset Monotonicity
NOISE AND CROSSTALK
Total Output Noise @ PGA Minimum
Total Output Noise @ PGA Maximum
Channel-to-Channel Crosstalk
@ 15 MSPS
@ 6 MSPS
POWER SUPPLY REJECTION
AVDD = 5 V 0.25 V
DIFFERENTIAL VREF (at 25°C)
CAPT–CAPB
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLIES
AVDD
DRVDD
OPERATING CURRENT
AVDD
DRVDD
Power-Down Mode
POWER DISSIPATION
3-Channel Mode
1-Channel Mode
–40
–65
4.75
3.0
5.0
5.0
75
5
200
400
300
(T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz, PGA
Gain = 1, Input range = 4 V p-p, unless otherwise noted.)
Min
Typ
30
30
18
16
±
16
±
0.5
Guaranteed
2.0/4.0
1.0
AVSS – 0.3
10
10
1
64
Guaranteed
–300
512
Guaranteed
3.0
9.0
70
90
0.1
2.0
+85
+150
5.25
5.25
+300
6
AVDD + 0.3
Max
Unit
MSPS
MSPS
MSPS
Bits
LSB
LSB
V p-p
V
V
pF
nA
V/V
Steps
mV
Steps
LSB rms
LSB rms
dB
dB
% FSR
V
°C
°C
V
V
mA
mA
μA
mW
mW
NOTES
1
Linear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp.
4V SET BY INPUT CLAMP
(3V OPTION ALSO AVAILABLE)
1V TYP
RESET TRANSIENT
4V p-p MAX INPUT SIGNAL RANGE
GND
2
The PGA Gain is approximately “linear in dB” and follows the equation:
G
ain =
1 + 5.0
6.0
63 – G
63
where
G
is the register value.
Specifications subject to change without notice.
–2–
REV. B
AD9826
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage, (I
OH
= 50
μA)
Low Level Output Voltage (I
OL
= 50
μA)
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
ADCCLK
= 15 MHz, f
CDSCLK1
= f
CDSCLK2
= 5 MHz,
C
L
= 10 pF, unless otherwise noted.)
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
I
OH
I
OL
V
OH
V
OL
Min
2.0
0.8
10
10
10
4.5
0.1
50
50
2.95
0.05
Typ
Max
Unit
V
V
μA
μA
pF
V
V
μA
μA
V
V
TIMING SPECIFICATIONS
(T
Parameter
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)
Symbol
t
PRA
t
PRB
t
ADCLK
t
C1
t
C2
t
C1C2
t
ADC2
t
C2ADR
t
C2ADF
t
C2C1
t
AD
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
RDV
t
OD
t
DV
t
HZ
Min
200
80
30
8
8
0
0
5
30
5
2
10
10
10
10
10
10
6
10
10
3 (Fixed)
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
CLOCK PARAMETERS
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-Up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
DATA OUTPUTS
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
NOTES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
REV. B
–3–
AD9826
ABSOLUTE MAXIMUM RATINGS*
With
Respect
To
Min Max
AVSS
AVSS
AVSS
DRVSS
DRVSS
DRVSS
–0.3
–0.3
–0.5
–0.5
–0.3
–0.3
–65
AVDD + 0.3
AVDD + 0.3
+6.5
+6.5
+0.3
DRVDD + 0.3
150
+150
300
Parameter
VIN, CAPT, CAPB
Digital Inputs
AVDD
DRVDD
AVSS
Digital Outputs
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
Unit
V
V
V
V
V
V
°C
°C
°C
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 5.3 mm SSOP
θ
JA
= 109°C/W
θ
JC
= 39°C/W
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
AD9826
PIN CONFIGURATION
CDSCLK1
1
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
(MSB) D7
D6
D5
2
3
4
5
6
7
28
AVDD
27
AVSS
26
VINR
25
OFFSET
24
VING
22
VINB
TOP VIEW
8
(Not to Scale)
21
CAPT
9
20
CAPB
19
AVSS
18
AVDD
17
SLOAD
16
SCLK
15
SDATA
AD9826
23
CML
D4
10
D3
11
D2
12
D1
13
(LSB) D0
14
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18, 28
19, 27
20
21
22
23
24
25
26
Mnemonic
CDSCLK1
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7
D6
D5
D4
D3
D2
D1
D0
SDATA
SCLK
SLOAD
AVDD
AVSS
CAPB
CAPT
VINB
CML
VING
OFFSET
VINR
Type
DI
DI
DI
DI
P
P
DO
DO
DO
DO
DO
DO
DO
DO
DI/DO
DI
DI
P
P
AO
AO
AI
AO
AI
AO
AI
Description
CDS Reference Level Sampling Clock
CDS Data Level Sampling Clock
A/D Converter Sampling Clock
Output Enable, Active Low
Digital Output Driver Supply
Digital Output Driver Ground
Data Output MSB. ADC DB15 High Byte, ADC DB7 Low Byte
Data Output. ADC DB14 High Byte, ADC DB6 Low Byte
Data Output. ADC DB13 High Byte, ADC DB5 Low Byte
Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
Data Output LSB. ADC DB8 High Byte, ADC DB0 Low Byte
Serial Interface Data Input/Output
Serial Interface Clock Input
Serial Interface Load Pulse
5 V Analog Supply
Analog Ground
ADC Bottom Reference Voltage Decoupling
ADC Top Reference Voltage Decoupling
Analog Input, Blue Channel
Internal Bias Level Decoupling
Analog Input, Green Channel
Clamp Bias Level Decoupling
Analog Input, Red Channel
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. B
–5–
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