www.fairchildsemi.com
LM555/NE555/SA555
Single Timer
Features
•
•
•
•
•
High Current Drive Capability (200mA)
Adjustable Duty Cycle
Temperature Stability of 0.005%/°C
Timing From
µSec
to Hours
Turn off Time Less Than 2µSec
Description
The LM555/NE555/SA555 is a highly stable controller
capable of producing accurate timing pulses. With a
monostable operation, the time delay is controlled by one
external resistor and one capacitor. With an astable
operation, the frequency and duty cycle are accurately
controlled by two external resistors and one capacitor.
8-DIP
Applications
•
•
•
•
Precision Timing
Pulse Generation
Time Delay Generation
Sequential Timing
1
8-SOP
1
Internal Block Diagram
R
R
R
8
GND
1
Vcc
Comp.
Trigger
Discharging Tr.
7
2
Discharge
Output
3
OutPut
Stage
F/F
6
Comp.
Threshold
Control
Voltage
Reset
4
5
Vref
Rev. 1.0.3
©2002 Fairchild Semiconductor Corporation
LM555/NE555/SA555
25°
Absolute Maximum Ratings (T
A
= 25
°
C)
Parameter
Supply Voltage
Lead Temperature (Soldering 10sec)
Power Dissipation
Operating Temperature Range
LM555/NE555
SA555
Storage Temperature Range
Symbol
V
CC
T
LEAD
P
D
T
OPR
T
STG
Value
16
300
600
0 ~ +70
-40 ~ +85
-65 ~ +150
Unit
V
°C
mW
°C
°C
2
LM555/NE555/SA555
Electrical Characteristics
(T
A
= 25°C, V
CC
= 5 ~ 15V, unless otherwise specified)
Parameter
Supply Voltage
Supply Current (Low Stable) (Note1)
Timing Error (Monostable)
Initial Accuracy (Note2)
Drift with Temperature (Note4)
Drift with Supply Voltage (Note4)
Timing Error (Astable)
Intial Accuracy (Note2)
Drift with Temperature (Note4)
Drift with Supply Voltage (Note4)
Control Voltage
Threshold Voltage
Threshold Current (Note3)
Trigger Voltage
Trigger Current
Reset Voltage
Reset Current
Symbol
V
CC
I
CC
Conditions
-
V
CC
= 5V, R
L
=
∞
V
CC
= 15V, R
L
=
∞
Min.
4.5
-
-
Typ.
-
3
7.5
Max.
16
6
15
Unit
V
mA
mA
ACCUR
∆t/∆T
∆t/∆V
CC
R
A
= 1kΩ to100kΩ
C = 0.1µF
-
1.0
50
0.1
3.0
0.5
%
ppm/°C
%/V
ACCUR
∆t/∆T
∆t/∆V
CC
V
C
V
TH
I
TH
V
TR
I
TR
V
RST
I
RST
R
A
= 1kΩ to 100kΩ
C = 0.1µF
V
CC
= 15V
V
CC
= 5V
V
CC
= 15V
V
CC
= 5V
-
V
CC
= 5V
V
CC
= 15V
V
TR
= 0V
-
-
V
CC
= 15V
I
SINK
= 10mA
I
SINK
= 50mA
V
CC
= 5V
I
SINK
= 5mA
V
CC
= 15V
I
SOURCE
= 200mA
I
SOURCE
= 100mA
V
CC
= 5V
I
SOURCE
= 100mA
-
2.25
150
0.3
10.0
3.33
10.0
3.33
0.1
1.67
5
0.01
0.7
0.1
-
%
ppm/°C
%/V
V
V
V
V
µA
V
V
µA
V
mA
V
V
V
V
V
V
ns
ns
nA
9.0
2.6
-
-
-
1.1
4.5
0.4
11.0
4.0
-
-
0.25
2.2
5.6
2.0
1.0
0.4
0.25
0.75
0.35
-
-
-
-
100
-
-
Low Output Voltage
V
OL
0.06
0.3
0.05
12.5
13.3
3.3
100
100
20
High Output Voltage
V
OH
12.75
2.75
-
-
-
Rise Time of Output (Note4)
Fall Time of Output (Note4)
Discharge Leakage Current
t
R
t
F
I
LKG
-
-
-
Notes:
1. When the output is high, the supply current is typically 1mA less than at V
CC
= 5V.
2. Tested at V
CC
= 5.0V and V
CC
= 15V.
3. This will determine the maximum value of R
A
+ R
B
for 15V operation, the max. total R = 20MΩ, and for 5V operation, the max.
total R = 6.7MΩ.
4. These parameters, although guaranteed, are not 100% tested in production.
3
LM555/NE555/SA555
Application Information
Table 1 below is the basic operating table of 555 timer:
Table 1. Basic Operating Table
Threshold Voltage
Trigger Voltage
Discharging Tr.
Reset(PIN 4)
Output(PIN 3)
(V
th
)(PIN 6)
(V
tr
)(PIN 2)
(PIN 7)
Don't care
Don't care
Low
Low
ON
V
th
> 2Vcc / 3
High
Low
ON
V
th
> 2Vcc / 3
High
-
-
Vcc / 3 < V
th
< 2 Vcc / 3 Vcc / 3 < V
th
< 2 Vcc / 3
V
th
< Vcc / 3
High
High
OFF
V
th
< Vcc / 3
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or
the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to
threshold voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr.
turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained
low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal
discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.
1. Monostable Operation
+Vcc
10
2
4
RESET
Trigger
8
Vcc
DISCH
R
A
=1
k
Ω
10
1
2
TRIG
THRES
Capacitance(uF)
10
0
6
C1
10
-1
3
OUT
GND
R
L
CONT
5
C2
10
-2
1
10
-3
10
-5
10
-4
R
10
-3
10
-2
10
-1
1M
10
0
10
M
10
1
A
A
7
10
0k
Ω
10
k
Ω
Ω
Ω
10
2
Time Delay(s)
Figure 1. Monoatable Circuit
Figure 2. Resistance and Capacitance vs.
Time delay(t
d
)
Figure 3. Waveforms of Monostable Operation
4
LM555/NE555/SA555
Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls
below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's
internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1
and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, V
C1
increases exponentially with the time constant t=R
A
*C and reaches 2Vcc/3
at td=1.1R
A
*C. Hence, capacitor C1 is charged through resistor R
A
. The greater the time constant R
A
C, the longer it takes
for the V
C1
to reach 2Vcc/3. In other words, the time constant R
A
C controls the output pulse width.
When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,
turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship
based on R
A
and C. Figure 3 shows the general waveforms during the monostable operation.
It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer
output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is
high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse
remains at below Vcc/3. Figure 4 shows such a timer output abnormality.
Figure 4. Waveforms of Monostable Operation (abnormal)
2. Astable Operation
+Vcc
100
R
A
(R
A
+2R
B
)
10
Ω
Ω
Ω
Ω
1k
4
RESET
8
Vcc
DISCH
Capacitance(uF)
Ω
Ω
Ω
k
Ω
1
10
7
R
B
1
Ω
k
Ω
00
0
0
10
2
TRIG
THRES
6
M
M
M
1M
Ω
Ω
0.1
M
M
M
M
10
Ω
Ω
Ω
Ω
3
R
L
OUT
GND
CONT
5
C2
C1
0.01
1
1E-3
100m
1
10
100
1k
10k
100k
Fr equency(Hz)
Figure 5. Astable Circuit
Figure 6. Capacitance and Resistance vs. Frequency
5
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论