ADuCM360/ADuCM361 Hardware User Guide
UG-367
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Using the
ADuCM360/ADuCM361
Low Power, Precision Analog Microcontroller
with Dual Sigma-Delta ADCs, ARM Cortex-M3
SCOPE
This user guide provides a detailed description of the
ADuCM360/ADuCM361
functionality and features.
DISCLAIMER
Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective owners.
DAC
AVDD
AGND
BUFFER
V
BIAS
GENERATOR
12-BIT
DAC
ON-CHIP
1.8V ANALOG
LDO
ON-CHIP
1.8V DIGITAL
LDO
POWER-ON
RESET
RESET
AIN0
AIN1
AIN2
AIN3
AIN4/IEXC
AIN5/IEXC
AIN6/IEXC
AIN7/VBIAS0/IEXC/
EXTREF2IN+
AIN8/EXTREF2IN–
AIN9/DACBUFF+
AIN10
AIN11/VBIAS1
MUX
V
REF
Σ-Δ
MODULATOR
24-BIT
Σ-Δ ADC
SINC3/4
FILTER
ON-CHIP
OSCILLATOR
(1% TYPICAL)
16MHz
ARM
CORTEX-M3
PROCESSOR
16MHz
GPIO PORTS
UART PORTS
2 × SPI PORTS
I
2
C PORTS
TIMER0
TIMER1
WATCHDOG
WAKE-UP TIMER
PWM
SERIAL WIRE
DEBUG,
PROGRAMMING
AND DEBUG
XTALO
XTALI
AMP
BUF
MOD2
GAIN
SINC2
FILTER
V
REF
Σ-Δ
MODULATOR
24-BIT
Σ-Δ ADC
SINC3/4
FILTER
MEMORY
128kB FLASH
8kB SRAM
19 GENERAL-
PURPOSE
I/O PORTS
AMP
BUF
MOD2
GAIN
DMA AND
INTERRUPT
CONTROLLER
DAC, TEMP,
IOVDD/4,
AVDD/4
SELECTABLE
V
REF
SOURCES
PRECISION
REFERENCE
SWDIO
SWCLK
ADuCM360
DVDD_REG
IREF
CURRENT
SOURCES
BUFFER
BUFFER
AVDD_REG
GND_SW
VREF– VREF+
INT_REF
IOVDD
IOVDD
Figure 1.
ADuCM360
Block Diagram
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. D | Page 1 of 176
10464-001
ADuCM360/ADuCM361 Hardware User Guide
TABLE OF CONTENTS
Scope .................................................................................................. 1
Disclaimer .......................................................................................... 1
Revision History ............................................................................... 4
Using the ADuCM360/ADuCM361 Hardware User Guide ....... 5
Number Notations ........................................................................ 5
Register Access Conventions ...................................................... 5
Acronyms and Abbreviations ..................................................... 5
Introduction to the ADuCM360/ADuCM361 ............................. 6
Main Features of ADuCM360/ADuCM361 ............................. 7
Memory Organization ................................................................. 9
Clocking Architecture .................................................................... 10
Clocking Architecture Features ................................................ 10
Clocking Architecture Block Diagram .................................... 10
Clocking Architecture Overview.............................................. 11
Clocking Architecture Operation............................................. 11
Clocking Architecture Memory Mapped Registers ............... 11
Power Management Unit ............................................................... 15
Power Management Unit Features ........................................... 15
Power Management Unit Overview......................................... 15
Power Management Unit Operation ........................................ 15
Power Management Unit Memory Mapped Registers .......... 16
Cortex-M3 Processor ..................................................................... 18
Cortex-M3 Processor Features ................................................. 18
Cortex-M3 Processor Overview ............................................... 18
Cortex-M3 Processor Operation .............................................. 18
Related Documents .................................................................... 19
ADC Circuit .................................................................................... 20
ADC Circuit Features ................................................................ 20
ADC Circuit Block Diagram..................................................... 20
ADC Circuit Overview .............................................................. 20
ADC Circuit Operation ............................................................. 21
Other ADC Support Circuits .................................................... 25
Other ADC Details..................................................................... 28
ADC Circuit Memory Mapped Registers ............................... 35
DAC .................................................................................................. 51
DAC Features .............................................................................. 51
DAC Overview............................................................................ 51
DAC Operation ........................................................................... 51
DAC DMA Operation................................................................ 53
DAC Memory Mapped Registers ............................................. 54
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System Exceptions and Peripheral Interrupts............................. 56
Cortex-M3 and Fault Management ......................................... 56
External Interrupt Configuration ............................................ 59
Interrupt Memory Mapped Registers ...................................... 59
DMA Controller ............................................................................. 64
DMA Features ............................................................................. 64
DMA Overview .......................................................................... 64
DMA Operation ......................................................................... 64
Error Management ..................................................................... 64
Interrupts ..................................................................................... 64
DMA Priority .............................................................................. 65
Channel Control Data Structure .............................................. 65
Control Data Configuration ..................................................... 66
DMA Transfer Types (CHNL_CFG[2:0]) ............................... 67
Address Calculation ................................................................... 69
DMA Memory Mapped Registers ............................................ 72
Flash Controller .............................................................................. 86
Flash Controller Features .......................................................... 86
Flash Controller Overview ........................................................ 86
Flash Memory Organization ..................................................... 86
Writing to Flash/EE Memory ................................................... 87
Erasing Flash/EE Memory ........................................................ 87
Flash Controller Performance and Command Duration ..... 88
Flash Protection .......................................................................... 88
Flash Controller Failure Analysis Key ..................................... 89
Flash Integrity Signature Feature ............................................. 89
Integrity of the Kernel................................................................ 89
Abort Using Interrupts .............................................................. 89
Flash Controller Memory Mapped Registers ......................... 90
Reset ................................................................................................. 99
Reset Features ............................................................................. 99
Reset Operation .......................................................................... 99
Reset Memory Mapped Registers .......................................... 100
Digital I/Os .................................................................................... 101
Digital I/Os Features ................................................................ 101
Digital I/Os Block Diagram .................................................... 101
Digital I/Os Overview.............................................................. 101
Digital I/Os Operation............................................................. 101
Digital Port Multiplex .............................................................. 103
GPIO Memory Mapped Registers.......................................... 104
Rev. D | Page 2 of 176
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I
2
C Serial Interface ....................................................................... 107
I
2
C Features ............................................................................... 107
I
2
C Overview............................................................................. 107
I
2
C Operation............................................................................ 107
I
2
C Operating Modes ............................................................... 109
I
2
C Memory Mapped Registers .............................................. 116
Serial Peripheral Interfaces ......................................................... 125
SPI Features ............................................................................... 125
SPI Overview ............................................................................ 125
SPI Operation ........................................................................... 125
SPI Transfer Initiation ............................................................. 126
SPI Interrupts ............................................................................ 128
Wire-OR’ed Mode (WOM) ..................................................... 128
CSERR Condition .................................................................... 129
SPI1 DMA ................................................................................. 129
SPI and Power-Down Modes ................................................. 133
SPI Memory Mapped Registers .............................................. 133
UART Serial Interface .................................................................. 138
UART Features ......................................................................... 138
UART Overview ....................................................................... 138
UART Operation ...................................................................... 138
Programmed I/O Mode........................................................... 138
Enable/Disable Bit .................................................................... 139
Interrupts................................................................................... 139
Buffer Requirements ................................................................ 139
DMA Mode ............................................................................... 139
UART Memory Mapped Registers......................................... 141
General-Purpose Timers ............................................................. 147
General-Purpose Timers Features ......................................... 147
General-Purpose Timers Block Diagram ............................. 147
ADuCM360/ADuCM361 Hardware User Guide
General-Purpose Timers Overview .......................................147
General-Purpose Timers Operation ......................................147
General-Purpose Timers Memory Mapped Registers .........149
Wake-Up Timer .............................................................................153
Wake-Up Timer Features .........................................................153
Wake-Up Timer Block Diagram .............................................153
Wake-Up Timer Overview ......................................................153
Wake-Up Timer Operation .....................................................153
Wake-Up Timer Memory Mapped Registers ........................155
Watchdog Timer............................................................................160
Watchdog Timer Features ........................................................160
Watchdog Timer Block Diagram ............................................160
Watchdog Timer Overview .....................................................160
Watchdog Timer Operation ....................................................160
Watchdog Timer Memory Mapped Registers .......................161
PWM ...............................................................................................163
PWM Features ...........................................................................163
PWM Overview ........................................................................163
PWM Operation .......................................................................163
PWM Interrupt Generation ....................................................167
PWM Memory Mapped Registers ..........................................167
Power Supply Support Circuits ...................................................170
Power Supply Support Circuits Features................................170
Hardware Design Considerations ...............................................171
Pin Configuration and Function Descriptions .....................171
Typical System Configuration .................................................174
Serial Wire Debug Interface ....................................................175
Related Links .................................................................................176
Rev. D | Page 3 of 176
ADuCM360/ADuCM361 Hardware User Guide
REVISION HISTORY
9/14—Rev. C to Rev. D
Moved Memory Section ................................................................ 11
Changes to ADC Circuit Overview Section ............................... 20
Changes to Digital Filter Option Section .................................... 28
Changes to Table 16 ........................................................................ 29
Changes to Table 30 ........................................................................ 41
Changes to Table 48 ........................................................................ 49
Changes to Figure 18 ...................................................................... 52
Changes to Table 65 ........................................................................ 66
Changes to Table 66 ........................................................................ 68
Changes to Table 67 ........................................................................ 69
Changes to Flash Protection: User Read Protection Section .... 88
Changes to I
2
C Features Section ................................................. 107
Changes to Table 131.................................................................... 117
Changes to Table 140.................................................................... 120
Changes to Table 141.................................................................... 121
Changes to Pin 36 and Pin 36 Description, Table 208 ............. 172
5/14—Rev. B to Rev. C
Change to Page 61 ...........................................................................61
7/13—Rev. A to Rev. B
Changes to Figure 1 ........................................................................... 1
Moved Revision History Section ..................................................... 4
Added Figure 2, Renumbered Sequentially; Changes to Single
12-Bit Voltage Output DAC Section .........................................................7
Changes to Memory Section ......................................................................8
Changes to Figure 3 .........................................................................10
Change to Table 4 ............................................................................11
Changes to Clocking Architecture Control Register 0 Section
and Table 5 ................................................................................................... 12
Changes to Power Management Unit Operation Section ..........13
Changes to ADC Circuit Overview Section and Figure 4 .........20
Changes to Analog Input Channel Configuration Section ........21
Removed Step Detection Circuit—Mode 1 Operation,
DETCON[3] = 1 Section ................................................................24
Changed Step Detection Circuit—Mode 0 Operation,
DETCON[3] = 0 Section to Step Detection Circuit Section;
Changes to Figure 7 Caption ..........................................................26
Changes to Bias Voltage (V
BIAS
) Generator Circuit Section,
Digital Filter Option Section, and Figure 10 ...............................28
Changes to Table 16 and Table 17; Added Simultaneous
Sampling Section .............................................................................29
UG-367
Changes to ADC Data Register Section and Figure 11 Caption .... 34
Changes to Bit 2, Table 22 .............................................................. 37
Changes to Offset Calibration Registers Section and Table 25 ....... 39
Changes to Bit 15 and Bit 14, Table 29 ......................................... 40
Changes to Table 42 and Table 43 ................................................. 47
Change to Bit 6, Table 48 ................................................................ 49
Changes to Figure 17....................................................................... 52
Change to DAC NPN Transistor Driver Mode, DACCON[8] =
1 Section............................................................................................ 53
Changes to Table 55 ........................................................................ 56
Changes to Flash Protection: User Read Protection Section .......... 88
Changes to Flash Controller System IRQ Abort Enable Register
Section and Table 109 ..................................................................... 95
Changes to Flash Controller System IRQ Abort Enable Register
Section and Table 110 ..................................................................... 97
Changes to Flash Controller System IRQ Abort Enable Register
Section and Table 111 ..................................................................... 98
Changes to I/O Pull-Up Enable Section ..................................... 101
Changes to I
2
C Overview Section ............................................... 107
Changes to DMA Mode Section ..................................................139
Changes to Bit 15, Table 169 ........................................................149
Changes to Interrupts/Wake-up Signals Section ...................... 155
Changes to Wake-Up Timer Compare Register A Section .......... 159
Changes to Watchdog Timer Clear Interrupt Register Section .... 162
Changes to PWM Section and Table 200 ................................... 163
Changes to Figure 33 and Table 201 ........................................... 164
Changes to Table 202 ....................................................................165
Changes to H-Bridge Mode Section, and Table 203 ................. 166
Changes to PWM Trip Function Interrupt Section and PWM
Output Pairs Interrupts Section ..................................................167
Changes to Table 205 ....................................................................168
Changes to Low Dropout Regulators Section............................ 170
Changes to Table 208 ....................................................................171
Changes to Figure 38.....................................................................174
Added Related Links Section .......................................................176
11/12—Rev. 0 to Rev. A
Changes to Pin 35 and Pin 36 Description ................................ 169
10/12—Revision 0: Initial Version
Rev. D | Page 4 of 176
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NUMBER NOTATIONS
Table 1. Number Notations
Notation
Bit N
V[X:Y]
0xNN
0bNN
NN
ADuCM360/ADuCM361 Hardware User Guide
USING THE
ADuCM360/ADuCM361
HARDWARE USER GUIDE
Description
Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.
Bit field representation covering Bit X to Bit Y of a value or a field (V).
Hexadecimal (Base 16) numbers are preceded by the prefix 0x.
Binary (Base 2) numbers are preceded by the prefix 0b'.
Decimal (Base 10) are represented using no additional prefixes or suffixes.
REGISTER ACCESS CONVENTIONS
Table 2. Register Access Conventions
Access
RW
R
W
Description
Memory location has read and write access.
Memory location is read access only. A read always returns 0, unless otherwise specified.
Memory location is write access only.
ACRONYMS AND ABBREVIATIONS
Table 3. Acronyms and Abbreviations
Acronym/Abbreviation
Σ-Δ
ADC
AF
AFE
ARM
CD
DMA
DSB
FSE
JTAG
LSB
MMR
MSB
NMI
NVIC
PGA
PMU
POR
PSM
PWM
RMS
Rx
SF
SIL
SPI
Tx
UART
Description
Sigma delta
Analog-to-digital converter
Averaging factor
Analog front end
Advanced RISC machine
Clock divider
Direct memory access
Data synchronization barrier
Full-scale error: gain error plus offset error
Joint test action group
Least significant byte/bit
Memory mapped register
Most significant byte/bit
Nonmaskable interrupt
Nested vectored interrupt controller
Programmable gain amplifier
Power management unit
Power-on reset
Power supply monitor
Pulse-width modulator
Root mean square
Receive
Sinc3/sinc4 filter
Safety integrity level
Serial peripheral interface
Transmit
Universal asynchronous transmitter
Rev. D | Page 5 of 176
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