Spartan-3 Generation
Configuration User
Guide
Extended Spartan-3A,
Spartan-3E, and Spartan-3
FPGA Families
UG332 (v1.6) October 26, 2009
R
R
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Spartan-3 Generation Configuration User Guide
www.xilinx.com
UG332 (v1.6) October 26, 2009
Revision History
The following table shows the revision history for this document.
Date
12/05/06
02/26/07
Version
1.0
1.1
Initial release.
Added configuration information for the
Spartan-3AN FPGA
family. Added
Chapter 10, “Internal Master SPI Mode”
describing how a Spartan®-3AN FPGA
configures from its internal In-System Flash memory. Increased
ConfigRate
settings for
Spartan-3A/3AN FPGAs based on improved data setup time (Table
4-11
and
Table 5-8).
Added links to new reference designs using the
Spartan-3E
and
Spartan-3A
Starter Kit
boards.
Added
Spartan-3A DSP
family configuration information. Added
“Bitstream Format,”
page 39.
Added
“Indirect SPI Programming using iMPACT,” page 134.
Updated
“Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration,”
page 172.
Updated JTAG ID values in
Table 12-4, page 249
. Added more information
to
“Configuration Watchdog Timer (CWDT) and Fallback,” page 289.
Noted in
“Non-Continuous SelectMAP Data Loading”
that
“Deasserting CSI_B”
is not
supported in the Spartan-3A, Spartan-3AN, and Spartan-3A DSP FPGA families.
Added
“Indirect Parallel Flash Programming Using iMPACT”.
Updated
Figure 5-14
to
showD[7:0] inputs clocked on rising CCLK edge. Added
“Byte Swapping”
description.
Added JTAG TAP Controller State descriptions in
Table 9-2.
Updated Spartan-3AN
FPGA Variant Select options in
Table 10-2.
Updated
Figure 14-20
and description to note
that MultiBoot Variant Select is based on Read Command from GENERAL2 register
when NEWMODE=1, not BOOTVSEL bits in MODE_REG. Updated software version
references throughout. Updated documentation links throughout.
Added
“Schedule of Figures”
and
“Schedule of Tables”.
Updated STMicroelectronics
and Intel Flash memory references to Numonyx. Noted HSWAP_EN is a dedicated pin
in the Spartan-3 family. Noted that Extended Spartan-3A family FPGA DOUT also
functions as BUSY as in Spartan-3/3E FPGAs. Noted that Extended Spartan-3A family
FPGAs do not support 1.8V configuration due to V
CCO2T
requirement of 2.0V. Updated
references to iMPACT indirect Flash programming support using Spartan-3 generation
devices.
Revision
05/23/07
1.2
11/21/07
1.3
07/01/08
1.4
UG332 (v1.6) October 26, 2009
www.xilinx.com
Spartan-3 Generation Configuration User Guide
Date
03/16/09
Version
1.5
Revision
(Cont’d)
Updated nomenclature for Extended Spartan-3A family. Added fifth paragraph below
“Overview and Design Considerations,” page 27.
Added
“Additional Resources,”
page 47,
and
“V
CCAUX
Level,” page 77.
Revised
Table 5-6, page 152, Figure 5-6,
page 160,
and
Figure 5-14, page 170.
Revised
Table 14-8, page 282.
Added
Chapter 17,
“Configuration Details”
and
Chapter 18, “Readback”.
Removed references to previous software version throughout document. Updated
“What I/O voltages are required in the end application?,” page 35
to indicate 1.8V
configuration is not recommended. Updated link to Command Line Tools User Guide
on
page 47.
Added
“I/O Behavior during PROG_B Activation,” page 56.
Updated
HSWAP_EN supply rail information in
Table 2-9, page 63
according to FPGA type.
Updated description for PROG_B in
Table 2-15, page 66.
Updated
“Default I/O
Standard During Configuration,” page 72
to include signal analysis recommendation.
Updated Output Drive in
“Default I/O Standard Setting During Configuration,”
page 72.
Updated
“Lowering VCCO_2 After Configuration in Extended Spartan-3A
Family,” page 73.
Updated
Figure 3-1, page 80.
Updated VCCO_2 comments for V
CCO
and V
CCJ
pins in
Table 3-1, page 80.
Updated VCCO_4 comments for V
CCO
pin in
Table 3-2, page 82.
Updated Step 10 under“Programming
via iMPACT,” page 96.
Removed link from first paragraph below
“Programming Support,” page 120.
Added
“Programming a Spartan-3AN FPGA,” page 121.
Updated
“Indirect SPI Programming
using iMPACT,” page 134.
Removed 1.8V I/O Voltage from
Table 5-8, page 161.
Updated
“Indirect Parallel Flash Programming Using iMPACT,” page 167.
Updated
Figure 7-1, page 178.
Updated
“Voltage Compatibility,” page 182.
Updated
“Voltage
Compatibility,” page 197.
Updated
“JTAG Cable Voltage Compatibility,” page 200,
Figure 5-1, page 144
and
Figure 5-2, page 145
to note that series resistors are not needed
for Extended Spartan-3A Family. Updated current-limiting resistors information in
Table 9-1, page 201
to note applicable families. Added Note 2 to
Table 9-3, page 204.
Added
“SUSPEND Pin,” page 218.
Updated
“ConfigRate: CCLK Frequency,” page 220.
Updated
Table 10-3, page 226, Table 10-4, page 229
and
Table 10-5, page 229
to note that
PROMGen assumes power-of-2 addressing. Updated the PROMGen -s size option
information in
“PROMGen,” page 228.
Added
“Programming Spartan-3AN FPGAs
Using SVF Files,” page 230.
Updated link to ISE Software Development System
Reference Guide on
page 233.
Added Configuration CRC Checking Options row to
Table 11-2, page 234.
Added
“Pre-Configuration Power-Up,” page 241, “Using the
Synchronization Word to Avoid Corrupted Data,” page 247
and
“Power-Down I/O
Behavior,” page 256.
Updated
“Startup,” page 251.
Removed reference to Spartan-3A
FPGA MultiBoot daisy chain in
Table 14-1, page 266.
Updated Step 14 on
page 286.
Updated information about unauthorized or unencrypted bitstreams
Table 15-4,
page 296.
Updated
“iMPACT Access to Device Identifier,” page 301.
Added
“Invalid
Bitstreams,” page 314.
Added
“INIT_B Functionality with iMPACT Software
Programming,” page 317.
Added information on SUSPEND pin to
Table 3-3, page 83,
Table 4-8, page 110, Table 5-3, page 148, Table 7-2, page 181,
and
Table 8-1, page 198.
10/26/09
1.6
Spartan-3 Generation Configuration User Guide
www.xilinx.com
UG332 (v1.6) October 26, 2009
Table of Contents
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Schedule of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schedule of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1: Overview and Design Considerations
15
21
Design Considerations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Will the FPGA load configuration data itself from external or internal memory or will an external
processor/microcontroller download configuration data?
. . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Does the application use a single FPGA or multiple FPGAs?
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Is the “easiest possible” configuration solution the more important consideration?
. . . . . . . . . . . . . . . . . . . . . .33
Will the application require a nonvolatile FPGA?
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Is the “lowest cost” solution the more important consideration?
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Is “fastest possible configuration time” the more important consideration?
. . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Will the FPGA or FPGAs be loaded with a single configuration image or loaded with multiple images?
. . . . .35
What I/O voltages are required in the end application?
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Will the FPGA application need to store nonvolatile data?
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Should the FPGA I/O pins be pulled High via resistors during configuration?
. . . . . . . . . . . . . . . . . . . . . . . . .35
Does the application target a specific FPGA density or should it support migrating to other FPGA densities in the
same package footprint?
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
What is the anticipated production lifetime for the end product?
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Do you want to protect your FPGA bitstream against unauthorized duplication?
. . . . . . . . . . . . . . . . . . . . . . .38
Do you want to load multiple FPGAs with the same configuration bitstream?
. . . . . . . . . . . . . . . . . . . . . . . . .38
Will the FPGA be used in a PCI™ application?
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Where to go for debugging support
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
FPGA Configuration Bitstream Sizes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Uncompressed Bitstream Image Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Bitstream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Synchronization Word
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Array ID
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Data Frames
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
CRC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Bitstream Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Setting Bitstream Options, Generating an FPGA Bitstream
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ISE Software Project Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
BitGen Command Line Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Additional Resources
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Chapter 2: Configuration Pins and Behavior during Configuration
General Configuration Control Pins
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Choose a Configuration Mode: M[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Spartan-3 Generation Configuration User Guide
UG332 (v1.6) October 26, 2009
www.xilinx.com
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