A p pl i c at i o n N o t e, V 1 . 1 , F e b . 20 0 7
6ED003L06-F
Gate Drive IC for three
phase conver ters -
Technical Description
AN-GateDriver-6ED003L06-1
Author: Wolfgang Frank
http://www.infineon.com/gatedriver
Power Management & Drives
N e v e r
s t o p
t h i n k i n g .
6ED003L06-F Gate Drive-IC
for three-phase converters
Revision History:
Previous Version:
Page
13
2007-2
1.1
V1.1
Subjects (major changes since last revision)
revised fig. 10
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Edition 2007-2
Published by Infineon Technologies AG,
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Infineon Technologies AG 2004.
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6ED003L06-F Gate Drive-IC
for three-phase converters
1
2
3
3.1
3.1.1
3.1.2
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.2
3.5.3
4
4.1
4.2
4.3
4.4
4.5
5
Short Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Technology Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Technical Description of 6ED003L06-F
. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Control Input Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Highside input pins (HIN), Lowside input pins (LIN) . . . . . . . . . . . . . . . . 7
Enable pin (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Control Output Section (/FAULT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
IC Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low Side Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
High Side Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Negative Transients at High Side Reference (pin VSx) . . . . . . . . . . . . . 12
Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overcurrent Protection (ITRIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Deadtime & Shoot Through Prevention . . . . . . . . . . . . . . . . . . . . . . . . . 14
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application of 6ED003L06-F
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC-supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Failure Reset (RCin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
17
17
18
Summary of Used Nomenclature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application Note
3
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
1
Short Description
The 6ED003L06-F is a high voltage gate drive IC for three-phase converters up to a
maximum blocking voltage of 600V. The converters can be used for example in drives
applications which are basing on induction machines (IM) or brushless DC motors. The
6ED003L06-F is designed in silicon-on-insulator-technology (SOI). This technology
provides a high ruggedness against negative voltage spikes and noise.
This application note gives an overview of the technological characteristics. It also
describes the most important sections in terms of the application and gives design
recommendations for a proper operation of the device in the application.
6ED003L06-F is similar to use as IR2136 and its derivates. It is compatible to the same
footprint, but not compatible in terms of the internal thresholds, which may concern the
external circuitry. Please refer here to the product specifications of 6ED003L06-F.
Application Note
4
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
2
Technology Characteristics
SOI is the abbreviation of
Silicon-On-Insulator
and is an advanced technique for MOS/
CMOS fabrications. It differs from the conventional bulk process by placing the active
transistor layer on the top of an insulator, as shown in
Figure 1.
Gate
Source
Doping
Doping-well
Poly-Si
Oxide
Doping-well
Buried Oxide
Silicon Substrate
Drain
Figure 1
Cross section of a FET in SOI-technology
The silicon is separated by a buried silicon oxide layer to one layer on the top and the
other on the bottom. The one on the top, which is the silicon film, is used to produce the
transistor and the one on the bottom is used as the silicon substrate. The buried silicon
oxide provides an insulation barrier between the active layer and silicon substrate and
hence reduces the parasitic capacitance tremendously. Moreover, this insulation barrier
disables leakage or latch-up currents between adjacent devices.
A major technological advantage of the Thin-Film-SOI technology is the easy way of
lateral insulation of elements inside the silicon film. The thin film technology allows each
device to be separated from all other devices by a simple local oxidation (LOCOS)
process. Thus, there is no need for CMOS-wells for preventing the "latch-up" effect and
reducing the chip size.
The small size of PN-junctions inside the thin silicon film leads to higher switching speed,
lower leakage currents and consequently higher temperature stability. In order to obtain
a proper body contact for the thin SOI-MOS transistor the channel doping is extended
and connected to a common source contact (split source contact). Hence the thin-film
SOI-MOS transistor exhibits an anti-paralleled diode that safeguards the device in case
of polarity reversal.
In spite of the thin drift regions inside the silicon films, reasonable low on-resistance per
area is achieved. This allows a cost effective layout of the output driver transistors.
The SOI technology is also implemented for the 600 V level-shift transistors and high-
voltage diodes. The 600V-NMOSFET is based on the low-voltage SOI-NMOSFET
structure in conjunction with a very long Drain-extension. The buried oxide insulation
barrier cuts off parasitic current paths between substrate and silicon film. This prevents
the latch-up effect even in case of high dv/dt switching under elevated temperature and
hence provides improved robustness.
Application Note
5
V1.1, 2007-2
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