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MSP430x5xx and MSP430x6xx Family Users Guide Literature Number SLAU208O June 2008Revised May 2015 Contents 14 Preface 52 System Resets Interrupts and Operating Modes System Control Module SYS 54 1 System Control Module SYS Introduction 55 11 System Reset and Initialization 55 12 121 Device Initial Conditions After System Reset 57 Interrupts 57 131 NonMaskable Interrupts NMIs 58 132 SNMI Timing 59 133 Maskable Interrupts 59 134 Interrupt Processing 59 135 Interrupt Nesting 61 136 Interrupt V......

MSP430x5xx and MSP430x6xx Family

User's Guide

Literature Number: SLAU208O

June 2008 – Revised May 2015

Contents

Preface

.......................................................................................................................................

System Resets, Interrupts, and Operating Modes, System Control Module (SYS)

.......................

1.1

1.2

1.3

System Control Module (SYS) Introduction

............................................................................

System Reset and Initialization

...........................................................................................

1.2.1 Device Initial Conditions After System Reset

..................................................................

Interrupts

....................................................................................................................

1.3.1 (Non)Maskable Interrupts (NMIs)

...............................................................................

1.3.2 SNMI Timing

.......................................................................................................

1.3.3 Maskable Interrupts

...............................................................................................

1.3.4 Interrupt Processing

...............................................................................................

1.3.5 Interrupt Nesting

...................................................................................................

1.3.6 Interrupt Vectors

...................................................................................................

1.3.7 SYS Interrupt Vector Generators

................................................................................

Operating Modes

...........................................................................................................

1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4

.............................................

1.4.2 Entering and Exiting Low-Power Modes LPMx.5

.............................................................

1.4.3 Extended Time in Low-Power Modes

..........................................................................

Principles for Low-Power Applications

..................................................................................

Connection of Unused Pins

...............................................................................................

Reset Pin (RST/NMI) Configuration

.....................................................................................

Configuring JTAG Pins

....................................................................................................

Boot Code

...................................................................................................................

Bootstrap Loader (BSL)

...................................................................................................

Memory Map – Uses and Abilities

.......................................................................................

1.11.1 Vacant Memory Space

..........................................................................................

1.11.2 JTAG Lock Mechanism Using the Electronic Fuse

..........................................................

JTAG Mailbox (JMB) System

............................................................................................

1.12.1 JMB Configuration

...............................................................................................

1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox

.................................................................

1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox

.......................................................................

1.12.4 JMB NMI Usage

..................................................................................................

Device Descriptor Table

...................................................................................................

1.13.1 Identifying Device Type

..........................................................................................

1.13.2 TLV Descriptors

..................................................................................................

1.13.3 Peripheral Discovery Descriptor

...............................................................................

1.13.4 CRC Computation

................................................................................................

1.13.5 Calibration Values

................................................................................................

1.13.6 Temperature Sensor Calibration for Devices With CTSD16

...............................................

SFR Registers

..............................................................................................................

1.14.1 SFRIE1 Register

.................................................................................................

1.14.2 SFRIFG1 Register

...............................................................................................

1.14.3 SFRRPCR Register

..............................................................................................

SYS Registers

..............................................................................................................

1.15.1 SYSCTL Register

................................................................................................

1.15.2 SYSBSLC Register

..............................................................................................

1.4

1.5

1.6

1.7

1.8

1.9

1.10

1.11

1.12

1.13

1.14

1.15

Contents

SLAU208O – June 2008 – Revised May 2015

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1.15.3

1.15.4

1.15.5

1.15.6

1.15.7

1.15.8

1.15.9

1.15.10

1.15.11

SYSJMBC Register

..............................................................................................

SYSJMBI0 Register

..............................................................................................

SYSJMBI1 Register

..............................................................................................

SYSJMBO0 Register

............................................................................................

SYSJMBO1 Register

............................................................................................

SYSUNIV Register

...............................................................................................

SYSSNIV Register

...............................................................................................

SYSRSTIV Register

............................................................................................

SYSBERRIV Register

..........................................................................................

Power Management Module and Supply Voltage Supervisor

...................................................

2.1

2.2

Power Management Module (PMM) Introduction

......................................................................

PMM Operation

...........................................................................................................

101

2.2.1 V

CORE

and the Regulator

.........................................................................................

101

2.2.2 Supply Voltage Supervisor and Monitor

......................................................................

101

2.2.3 Supply Voltage Supervisor and Monitor - Power-Up

........................................................

107

2.2.4 Increasing V

CORE

to Support Higher MCLK Frequencies

...................................................

108

2.2.5 Decreasing V

CORE

for Power Optimization

....................................................................

109

2.2.6 Transition From LPM3 and LPM4 Modes to AM

............................................................

109

2.2.7 LPM3.5 and LPM4.5

............................................................................................

109

2.2.8 Brownout Reset (BOR), Software BOR, Software POR

....................................................

110

2.2.9 SVS and SVM Performance Modes and Wakeup Times

..................................................

110

2.2.10 PMM Interrupts

..................................................................................................

113

2.2.11 Port I/O Control

.................................................................................................

113

2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional)

......................................................

113

PMM Registers

............................................................................................................

114

2.3.1 PMMCTL0 Register

..............................................................................................

115

2.3.2 PMMCTL1 Register

..............................................................................................

116

2.3.3 SVSMHCTL Register

............................................................................................

117

2.3.4 SVSMLCTL Register

............................................................................................

118

2.3.5 SVSMIO Register

................................................................................................

119

2.3.6 PMMIFG Register

................................................................................................

120

2.3.7 PMMRIE Register

................................................................................................

122

2.3.8 PM5CTL0 Register

..............................................................................................

123

Battery Backup Introduction

.............................................................................................

Battery Backup Operation

...............................................................................................

3.2.1 Activate Access to Backup-Supplied Subsystem

............................................................

3.2.2 Manual Switching

................................................................................................

3.2.3 Disable Switching

................................................................................................

3.2.4 Measuring the Supplies

.........................................................................................

3.2.5 LPMx.5 and Backup Operation

................................................................................

3.2.6 Resistive Charger

................................................................................................

Battery Backup Registers

................................................................................................

3.3.1 BAKCTL Register

................................................................................................

3.3.2 BAKCHCTL Register

............................................................................................

Auxiliary Supply System Introduction

..................................................................................

Auxiliary Supply Operation

..............................................................................................

4.2.1 Startup

.............................................................................................................

4.2.2 Switching Control

................................................................................................

4.2.3 Software-Controlled Switching

.................................................................................

4.2.4 Hardware-Controlled Switching

................................................................................

4.2.5 Interactions Among f

SYS

, V

CORE

, V

DSYS

, SVM

, and AUXxLVL

...............................................

Contents

2.3

Battery Backup System

.....................................................................................................

124

3.1

3.2

125

126

127

128

129

130

131

133

134

135

136

137

3.3

Auxiliary Supply System (AUX)

..........................................................................................

132

4.1

4.2

SLAU208O – June 2008 – Revised May 2015

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4.3

4.2.6 Auxiliary Supply Monitor

........................................................................................

4.2.7 LPMx.5 and Auxiliary Supply Operation

......................................................................

4.2.8 Digital I/Os and Auxiliary Supplies

.............................................................................

4.2.9 Measuring the Supplies

.........................................................................................

4.2.10 Resistive Charger

...............................................................................................

4.2.11 Auxiliary Supply Interrupts

.....................................................................................

4.2.12 Software Flow

...................................................................................................

4.2.13 Examples of AUX Operation

..................................................................................

AUX Registers

.............................................................................................................

4.3.1 AUXCTL0 Register

..............................................................................................

4.3.2 AUXCTL1 Register

..............................................................................................

4.3.3 AUXCTL2 Register

..............................................................................................

4.3.4 AUX2CHCTL Register

..........................................................................................

4.3.5 AUX3CHCTL Register

..........................................................................................

4.3.6 AUXADCCTL Register

..........................................................................................

4.3.7 AUXIFG Register

................................................................................................

4.3.8 AUXIE Register

..................................................................................................

4.3.9 AUXIV Register

..................................................................................................

Unified Clock System (UCS) Introduction

.............................................................................

UCS Operation

............................................................................................................

5.2.1 UCS Module Features for Low-Power Applications

.........................................................

5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

................................................

5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO)

..........................................

5.2.4 XT1 Oscillator

....................................................................................................

5.2.5 XT2 Oscillator

...................................................................................................

5.2.6 Digitally Controlled Oscillator (DCO)

..........................................................................

5.2.7 Frequency Locked Loop (FLL)

.................................................................................

5.2.8 DCO Modulator

..................................................................................................

5.2.9 Disabling FLL Hardware and Modulator

......................................................................

5.2.10 FLL Operation From Low-Power Modes

.....................................................................

5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules

................................

5.2.12 UCS Module Fail-Safe Operation

.............................................................................

5.2.13 Synchronization of Clock Signals

.............................................................................

Module Oscillator (MODOSC)

...........................................................................................

5.3.1 MODOSC Operation

............................................................................................

UCS Registers

............................................................................................................

5.4.1 UCSCTL0 Register

..............................................................................................

5.4.2 UCSCTL1 Register

..............................................................................................

5.4.3 UCSCTL2 Register

..............................................................................................

5.4.4 UCSCTL3 Register

..............................................................................................

5.4.5 UCSCTL4 Register

..............................................................................................

5.4.6 UCSCTL5 Register

..............................................................................................

5.4.7 UCSCTL6 Register

..............................................................................................

5.4.8 UCSCTL7 Register

..............................................................................................

5.4.9 UCSCTL8 Register

..............................................................................................

5.4.10 UCSCTL9 Register

.............................................................................................

MSP430X CPU (CPUX) Introduction

...................................................................................

Interrupts

...................................................................................................................

CPU Registers

............................................................................................................

6.3.1 Program Counter (PC)

..........................................................................................

6.3.2 Stack Pointer (SP)

...............................................................................................

139

141

142

143

145

146

148

149

150

151

152

153

154

155

156

157

159

161

162

163

164

165

166

167

168

171

172

173

174

175

176

177

178

179

181

183

184

185

187

189

190

Unified Clock System (UCS)

...............................................................................................

158

5.1

5.2

5.3

5.4

CPUX

..............................................................................................................................

186

6.1

6.2

6.3

Contents

SLAU208O – June 2008 – Revised May 2015

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6.4

6.5

6.6

6.3.3 Status Register (SR)

............................................................................................

6.3.4 Constant Generator Registers (CG1 and CG2)

.............................................................

6.3.5 General-Purpose Registers (R4 to R15)

......................................................................

Addressing Modes

........................................................................................................

6.4.1 Register Mode

....................................................................................................

6.4.2 Indexed Mode

....................................................................................................

6.4.3 Symbolic Mode

...................................................................................................

6.4.4 Absolute Mode

...................................................................................................

6.4.5 Indirect Register Mode

..........................................................................................

6.4.6 Indirect Autoincrement Mode

...................................................................................

6.4.7 Immediate Mode

.................................................................................................

MSP430 and MSP430X Instructions

...................................................................................

6.5.1 MSP430 Instructions

............................................................................................

6.5.2 MSP430X Extended Instructions

..............................................................................

Instruction Set Description

...............................................................................................

6.6.1 Extended Instruction Binary Descriptions

.....................................................................

6.6.2 MSP430 Instructions

............................................................................................

6.6.3 Extended Instructions

...........................................................................................

6.6.4 Address Instructions

.............................................................................................

Flash Memory Introduction

..............................................................................................

Flash Memory Segmentation

............................................................................................

7.2.1 Segment A

........................................................................................................

Flash Memory Operation

................................................................................................

7.3.1 Erasing Flash Memory

..........................................................................................

7.3.2 Writing Flash Memory

...........................................................................................

7.3.3 Flash Memory Access During Write or Erase

................................................................

7.3.4 Stopping Write or Erase Cycle

.................................................................................

7.3.5 Checking Flash Memory

........................................................................................

7.3.6 Configuring and Accessing the Flash Memory Controller

..................................................

7.3.7 Flash Memory Controller Interrupts

...........................................................................

7.3.8 Programming Flash Memory Devices

.........................................................................

FCTL Registers

...........................................................................................................

7.4.1 FCTL1 Register

..................................................................................................

7.4.2 FCTL3 Register

..................................................................................................

7.4.3 FCTL4 Register

..................................................................................................

7.4.4 SFRIE1 Register

.................................................................................................

MID Overview

.............................................................................................................

Flash Memory With MID Support

.......................................................................................

MID Parity Check Logic

..................................................................................................

Detecting Unprogrammed Memory Accesses

........................................................................

MID ROM

..................................................................................................................

MID Support Software Function

........................................................................................

8.6.1 MidEnable() Function

............................................................................................

8.6.2 MidDisable() Function

...........................................................................................

8.6.3 MidGetErrAdr() Function

........................................................................................

8.6.4 MidCheckMem() Function

......................................................................................

8.6.5 MidSetRaw() Function

...........................................................................................

8.6.6 MidGetParity() Function

.........................................................................................

8.6.7 MidCalcVParity() Function

......................................................................................

User's UNMI Interrupt Handler

..........................................................................................

192

193

194

196

197

198

203

207

209

210

211

213

218

229

230

232

284

327

343

344

345

346

350

357

358

359

360

361

362

363

364

365

367

368

369

370

371

372

373

Flash Memory Controller

...................................................................................................

342

7.1

7.2

7.3

7.4

Memory Integrity Detection (MID)

........................................................................................

366

8.1

8.2

8.3

8.4

8.5

8.6

8.7

SLAU208O – June 2008 – Revised May 2015

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