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iPhone 5S 820-3292-A ____NoRestriction1 3G版.pdf

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电路图

苹果全系列图纸：iPhone  5S  820-3292-A  ____NoRestriction1  3G版.pdf

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LCM
TO
AP PIFA
RDAR:
//12858364
BOARD_REV2
BOARD_REV
1
BOARD INFO
M
BOARD INFO
R
GPI035
AR1
6
AT
16
oo
cu
SC
GPI036
GPI037
GPI038
ACCESSORY
UART:
TOLERANCE
1.98V
16
18
TOUCH TO
__AP_SP
1
MISO
1
AU5
1_MI
SO
SP
I
l_MOS
I
SP
I
BOARD REVO
CO
REMOVED
AP_TO_NAVA
JO
NET
REMOVED
R146
PU
FROM NAVAJO
Ncfÿi—
M
o
a
Q
UART
6_RXD
W31
TRISTAR
TO
AP
ACC
UART
6
RXD
18
AP
TO
TOUCH
SPI1
MOSI
AV4
AU4
AR5
AU
6
GRAPE
UART
6
TXD
16
18
AP
TO TOUCH
SPI1
CLK
SPI1_SCLK
1_SS
IN
SP
I
CO
REMOVED
PU
FROM NAVAJO
>
RDAR//12853395
18
AP
TO TOUCH
SPI1
CS
L
RDAR//12853395
MAKE
SURE THIS
GPIO
ISN'T
FLOATING
ROOM=H6P
NAVAJO
17
R399
33.2
1/32W
MF
NAVAJO TO
AP
SP
12
MISO
2_MI
SO
SP
I
SPl2_MOSI
2
AP
TO
NAVAJO
SP
I
MOSI
AP
NAVAJO TO
PMU
INT H
AR6
AP7
AN
8
NOTE:
THIS
PULLUP
+
NET
FOR NAVAJO
DAISY-CHAIN
(
PROTOl
A/PROT02
)
TO
BE DELETED
FROM
DESIGN
WHEN
NAVAJO SILICON
ARRIVES.
PULLDOWN
NEEDED
ON
FORCE_DFU
FOR
AO ROM.
CAN
BE
REMOVED
WHEN
GET
B0
SILICON
RDAR:
//12963383
FORCE
DFU
17
AP
TO NAVAJO
SPI2
CLK
PMr
1%
01005
TO NAVAJO
SPI2
CLK
R
SPI2_SCLK
SPI2_SSIN
CHANGE
R93
TO
XWLINK
XW93
TO
STILL
ENABLE
PROBING
REMOVED
R53
(HAS
BEEN
NOSTUFF
SINCE
EVT1)
RDAR:
//12963380
XW93
SM
10
10
10
10
CODEC TO
AP
SP
I
MISO
3
TO CODEC
SP
I
CLK
3
AV10
3_MI
SO
SP
I
3_MOS
I
SP
I
3_SCLK
SP
I
AP
TO
PMU
SOCHOT1
H6P
AP
TO
PMU
SOCHOT1
13
CODEC
3
AP
TO CODEC
SP
I
MOSI
AP
ANl
2
ATI
0
PLACE
XW93
ON OUTER
LAYER
B
3
AP
TO CODEC
SP
I
CS
L
AP
11
SP
I
3
SS
IN
B
XR1
62
10
OK
1/32W
MF
5%
01005
NOSTUFF
MENU
&
POWER
/
HOLD
KEY
BUFFER
BOOTSTRAPPING
FLOAT=LOW,
(
BOARD_RE
V
,
BOARD_ID,
GPI036,
GPI037}
23
12
PP1V8
ALWAYS
BOOT_OFG)
PCB
:
PLACE
THIS
TOP
SIDE
,
NORTH
END
OF
SINGLE_BRD
392K
1/32W
01005
U25
7
4LVC1G34GX
SOT1226
BOARD_REV
[
3
:
0
]
=
{
GPI034
,
GPI035,
PULLUP=HIGH
COMMON
PULL UP
FOR
BOARD_REV,
|
_
££
1
y
£
R12
1
00K
1/32W
BOARD_ID
AND
BOOT_CONFIG
PINS
2
3
5
6
7
21
23
10
11
12
14
16
18
19
1111
1110
1101
1100
1011
1010
PROT02
/2
A,
TRI
SAR/L1
9
EVT1
MAIN
BUILD
EVT1
MESA
BUILD
EVT1A
MESA
BUILD
E1B
MAIN
BUILD
E1C
MAIN
BUILD
<
BUTTON TO
AP
HOLD
KEY L
ÿ
4
BUTTON TO
AP
HOLD
KEY
BUFF
L
3
13
BOARD_ID
[3:0]
=
{
GP
IOl
6
,
SPIOO_MISO,
FLOAT=LOW,
PULLUP=HIGH
0000
0001
A
0010
0011
XI4
5
XI
4
5
XI
52
XI
52
MLB
<
DEV
MLB
DEV
---
---
.
Nd_
SELECTED
(NOSTUFF
R3000
&
STUFF
R3001)
01005
•>
BOARD INFO
SPIO_MOSI,
SPI0_SCLK}
R12
MUST
WIN
OVER
6X
INTERNAL
PULL-DOWNS
THAT ARE
BOARD
INFO
3
_
0%
100K
2io"
16
14
DPP1V8
12
SDRAM
SELECTED
ÿ3000
PCB: PLACE THIS
BOTTOM
SIDE,
SOUTH
END
OF
SINGLE
BRD
3
92K
1/32W
01005
o
.00
MF
U2 6
7
4LVC1G34GX
SOT1226
4
BUTTON TO
AP
MENU
KEY
BUFF
L
3
13
1/32W
7
BUTTON TO
AP
MENU
KEY L
01005
BOARD INFO
R
NOSTUFF
BOOT_CONFIG
[3:0]
=
{
GP
102
9_CONFIG3
,
GP
102
8_CONF
IG2
,
GP
102
5_CONFIGl
,
GP
IOl8_CONF
IG0
}
FLOAT=LOW,
_
BOARD
o
.00
o%
MF
INFO
3
PULLUP=HIGH
NG-L
0000
0001
0010
0011
SPI0
SPI0
TEST
MODE
NAND
NAND
TEST
MODE
2R3
0 01
<
---
1/32W
SELECTED
„
01005
BOARD INFO
M
8
7
6
5
4
3
8
7
6
5
4
3
2
1
H6P
24
2 1
GND, VDDCA,
VDDCA,
RESET
1V8
L
VDDl/2,
VDD
,
VDD_CPU,
VDD
GPU
VDD
G30
G31
G33
23
12
VDD
1 2
,
VDDQ
/
VDD
_
CPU
,
VDD_GPU
23
NOTE:
CKEIN
CONFIRMED
1.8V
TOLERANT
ON
5/6/12,
BY
MANU
G
t
AP22
U32
DDR0_CKE
IN
DDR1
CKEIN
pfi
Yip
r
nor
CI
7 7
20%
4V
X5R-CERM
0610
ROOM=H6P
T
12
gUU
PP""
D
0
1UF
6.
3V
X5R-CERM
20%
C41
.
t
45
DDRQ
ZQ
45
DDR1
ZO
DDR0.
VDD_CKE
(
<
IMA)
U31
DDR1.
_VDD_CKE
(
<
1MA
)
AU1
5
DDR0.
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AC
3 3
AP23
OMIT
TABLE
HI
H2
H3
H4
H5
H25
4
.
3UF
CI
4
1
20%
4V
X5R-CERM
0610
ROOM=H6P
C151
ÿA7_
AAl
7
.19
r
•
4
DDR1
RREF_CA
01005
ROOM=H6P
DDR0.
_RREF_DQ
DDR1.
_RREF__DQ
T
4
M28
P26
R25
15
SYM
10
OF
13
T18
co
m
Fll
AU1
7
2R7
3
XR7
2
•
ÿ
243
i%
ÿ
•
1/32W
MF
;
,
243
i%
MF
4.45
DDR1
VREF
4
4
CA
Y33
D14
U4
AB34
AF34
ÿ
-
45
DDRO
VREF
Q
O
45
DDR1
VREF
DQ
1/32W
ROOM=H6P
DDR0.
DDR1.
DDR0.
VREF_CA
VREF_CA
VREF_DQ
H27
H29
H32
i
1
I
-
4
2
2
.
3UF
U1
H
6P
POP-
1GB
-DDR
SC58960X01-A030
T1
20%
6.3V
CERM-X5R
0402-2
P,OOM=H6P
OUF
CI
0
7
4
.
3UF
20%
4V
X5R-CERM
0610
PxOOM=H6P
I
4
Cl
52
r
7
.
3UF
20%
4V
Cl
7
3
20%
4V
X6S
0204
ROOM=H6P
1
X5R-CERM
0610
ROOM=H6P
I
AA21
AA2
3
1UF
- -
1UF
Cl
53
C158-
1UF\
20%
)
4
V
/
CERM
0402
ROOM=H6P
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r
L
—
_
20%
4V
2
X6S
z
0204
ROOM=H6P
Cl
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ro
0
.
47UF\
20%
)
6.3
V
CERM
T
/
CN
4
0402
ROOM=H6P
<•
L2
9
FCMSP
OMIT
TABLE
Tlÿ
4
C1
2
20%
CI
60
20%
4V
X5R-CERM
0610
ROOM=H6P
0
1UF
6.3V
X5R-CERM
.
.
3UF
01005
ROOM=H6P
2
01005
ROOM=H6P
?
01005
DDR1
VREF_DQ
J2
J3
V22
H6PPOP-1GB-DDR
SC58960X01-AO
30
(CURRENT
CONSUMPTION
SHARED
WITH
VDDIOD)
晓
培 军
训 苹
咨 果
询 技
QQ 术
： 论
99 坛
71 ww
66 w.
52 ip
4 ap
pl
e.
OMIT
TABLE
OMIT
TABLE
U1
J4
AB30
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AH20
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Ulÿ
23
12
?ivi
fni
t
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H6PPOP-
1GB-DDR
SC58
960X01
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30
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IMPEDANCE
CONTROL)
AV12
J6
ROOM=H6P
ROOM=H6P
U19
FCMSP
J8
C282
1UF
20%
4V
CERM
CI
6 9
1UF
20%
C75
20%
1OUF
6.3V
ROOM=H6P
C80
20%
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1
6.3V
ROOM=H6P
AA25
AA27
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9
VDDCA
SYM
7
OF
13
J10
K20
:24
FCMSP
OMIT_TABLE
CERM-X5R
CERM-X5R
4
V
AV21
R34
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23
21
12
J12
CERM
K22
0402-2
0402-2
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13
OF
13
J14
0402
0402
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ÿB22
AB24
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AC
15
J16
1
3
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3
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6
r
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20%
r
J18
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2
i
-
—
?
2
C285
20%
T
ÿ
4
.
3UF_
4V
0610
ROOM=H6P
-
1UF
20%
4
V
X6S
0204
C53
T
AC2
J20
_L
4
.
3UF
ROOM=H6P
C133
4
4
V
X5R-CEPM
20%
.
3UF
AB28
21
AC23
C49
20%
4
V
X6S
0204
4V
X5R-CERM
1UF
J24
LI1
0610
0610
ROOM=H6F
AC25
ÿ
X5R-CERM
ROOM=H6P
T
—
?
2
J2 6
ROOM=H
6P
ROOM=H6P
Ll3
27
J2 8
ROOM=H6P
J30
0
.
47UF
20%
CI
7
4
CERM
0
.
47UF
20%
CI
6 6
6.3V
CERM
ADt
AD1
4
W7|
ROOM=H6P
AC29
ROOM
ROOM=H6P
VSS
J31
c
F
i
Kl
K2
C59
20%
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X7S
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0402
3
1
'
Z
0
.
47UF
VDD2
K3
--
-
X
6.3V
W17
C87
Cl2
1UF
20%
4V
CERM
AD22
'27
0402
1
—
'
4
3
L25
2
K4
0204
ROOM=H6P
K5
i
L27
1
(VDD
BALLS
=
VDD_SOC
-
--
10
AUl
4
AU20
AU22
K7
VDD
K9
Kl
1
Kl3
Kl5
2,
50 0MA
FOR
VDD_SOC
0125C
01
OV
VDD
--
V4
20%
1UF
4
V
CERM
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AF22
0402
0402
0402
3
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5
AG23
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.
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7
C4
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7
7
,
50
OMA FOR
G3
GPU
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CI
4
Kl
9
0125C
01
IV
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6
.
K21
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3
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5
•
17
16
14 12
10
3.
24
AF30
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AJ2
3
'2
5
ROOM=H6P
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T
AE34
10,80
OMA
FOR
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+
1
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01
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.
.
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3
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9
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0
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C100
.
0
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20%
6.3V
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0402
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0
.
47UF
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C97
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22
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3
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0
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2
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T
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4
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V
X7S
0204
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45_BUCK0_FB
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7
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3
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