元器件交易½www.cecb2b.com
2-Channel, 2.35 V to 5.25 V
250 kSPS, 10-/12-Bit ADCs
AD7911/AD7921
FEATURES
Fast throughput rate: 250 kSPS
Specified for V
DD
of 2.35 V to 5.25 V
Low power:
4 mW typ at 250 kSPS with 3 V supplies
13.5 mW typ at 250 kSPS with 5 V supplies
Wide input bandwidth:
71 dB minimum SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 µA maximum
8-lead TSOT package
8-lead MSOP package
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN0
MUX
V
IN1
T/H
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
SCLK
CS
AD7911/AD7921
CONTROL LOGIC
DOUT
04350-0-001
DIN
GND
APPLICATIONS
Battery-powered systems:
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
Figure 1.
The AD7911/AD7921 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from V
DD
, thereby
allowing the widest dynamic input range to the ADC. The
analog input range for the part, therefore, is 0 to V
DD
. The
conversion rate is determined by the SCLK signal.
GENERAL DESCRIPTION
The AD7911/AD7921
1
are 10-bit and 12-bit, high speed, low
power, 2-channel successive approximation ADCs, respectively.
The parts operate from a single 2.35 V to 5.25 V power supply
and feature throughput rates of up to 250 kSPS. The parts
contain a low noise, wide bandwidth track-and-hold amplifier,
which can handle input frequencies in excess of 6 MHz. The
conversion process and data acquisition are controlled using CS
and the serial clock, allowing the devices to interface with
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The channel to be converted is selected through the DIN pin,
and the mode of operation is controlled by CS. The serial data
stream from the DOUT pin has a channel identifier bit, which
provides information about the converted channel.
1
PRODUCT HIGHLIGHTS
1.
2.
3.
2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package.
Low power consumption.
Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock;
conversion time is reduced when the serial clock speed is
increased. The parts also feature a power-down mode to
maximize power efficiency at lower throughput rates.
Average power consumption is reduced when the power-
down mode is used while not converting. Current
consumption is 1 µA maximum and 50 nA typically when
in power-down mode.
Reference derived from the power supply.
No pipeline delay.
The parts feature a standard successive approximation
ADC with accurate control of the sampling instant via a CS
input and once-off conversion control.
4.
5.
Protected by U.S. Patent Number 6,681,332.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
元器件交易½www.cecb2b.com
AD7911/AD7921
TABLE OF CONTENTS
Specifications..................................................................................... 3
AD7911 Specifications................................................................. 3
AD7921 Specifications................................................................. 5
Timing Specifications .................................................................. 7
Timing Diagrams.......................................................................... 7
Timing Examples.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 13
Circuit Information ........................................................................ 15
Converter Operation.................................................................. 15
ADC Transfer Function............................................................. 15
Typical Connection Diagram ................................................... 16
Analog Input ............................................................................... 16
Digital Inputs .............................................................................. 17
DIN Input .................................................................................... 17
DOUT Output ............................................................................ 17
Modes of Operation ....................................................................... 18
Normal Mode.............................................................................. 18
Power-Down Mode .................................................................... 18
Power-Up Time .......................................................................... 19
Power vs. Throughput Rate....................................................... 20
Serial Interface ................................................................................ 21
Microprocessor Interfacing....................................................... 22
Application Hints ........................................................................... 24
Grounding and Layout .............................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 28
元器件交易½www.cecb2b.com
AD7911/AD7921
SPECIFICATIONS
AD7911 SPECIFICATIONS
Temperature range for A Grade from −40°C to +85°C.
V
DD
= 2.35 V to 5.25 V, f
SCLK
= 5 MHz, f
SAMPLE
= 250 kSPS; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to- Noise and Distortion (SINAD)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise (SFDR)
2
Intermodulation Distortion (IMD)
2
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
2
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
2
Differential Nonlinearity
2
Offset Error
2
Offset Error Match
2, 3
Gain Error
2
Gain Error Match
2, 3
Total Unadjusted Error (TUE)
2
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
A Grade
1
61
−71
−72
−82
−83
10
30
−90
8.5
1.5
10
±0.5
±0.5
±0.5
±0.3
±0.5
±0.3
±0.5
0 to V
DD
±0.3
20
0.7 (V
DD
)
2
0.3
0.2 (V
DD
)
0.8
±0.3
±0.3
±0.3
5
V
DD
− 0.2
0.2
±0.3
5
Unit
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V
µA max
pF typ
V min
V min
V max
V max
V max
µA max
µA max
µA max
pF max
V min
V max
µA max
pF max
Straight (natural) binary
2.35 V ≤ V
DD
≤ 2.7 V
2.7 V < V
DD
≤ 5.25 V
V
DD
= 2.35 V
2.35 V < V
DD
≤ 2.7 V
2.7 V < V
DD
≤ 5.25 V
V
IN
= 0 V or V
DD
fa = 100.73 kHz, fb = 90.7 kHz
fa = 100.73 kHz, fb = 90.7 kHz
Test Conditions/Comments
f
IN
= 100 kHz sine wave
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 10 bits
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
, CS Pin
Input Current, I
IN
, DIN Pin
Input Capacitance, C
IN
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
See notes at end of table.
I
SOURCE
= 200 µA, V
DD
= 2.35 V to 5.25 V
I
SINK
= 200 µA
Rev. 0 | Page 3 of 28
元器件交易½www.cecb2b.com
AD7911/AD7921
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
2
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode (Static)
Full Power-Down Mode (Dynamic)
Power Dissipation
4
Normal Mode (Operational)
Full Power-Down
A Grade
1
2.8
290
250
2.35/5.25
3
1.5
4
2
1
0.38
0.2
20
6
5
Unit
µs max
ns max
kSPS max
V min/max
mA typ
mA typ
mA max
mA max
µA max
mA typ
mA typ
mW max
mW max
µW max
Digital I/Ps = 0 V or V
DD
V
DD
= 4.75 V to 5.25 V, SCLK on or off
V
DD
= 2.35 V to 3.6 V, SCLK on or off
V
DD
= 4.75 V to 5.25 V, f
SAMPLE
= 250 kSPS
V
DD
= 2.35 V to 3.6 V, f
SAMPLE
= 250 kSPS
SCLK on or off, typically 50 nA
V
DD
= 5 V, f
SCLK
= 5 MHz, f
SAMPLE
= 25 kSPS
V
DD
= 3 V, f
SCLK
= 5 MHz, f
SAMPLE
= 25 kSPS
V
DD
= 5 V, f
SAMPLE
= 250 kSPS
V
DD
= 3 V, f
SAMPLE
= 250 kSPS
V
DD
= 5 V
Test Conditions/Comments
14 SCLK cycles with SCLK at 5 MHz
1
2
Operational from V
DD
= 2 V, with V
IH
= 1.9 V minimum and V
IL
= 0.1 V maximum.
See the Terminology section.
3
Guaranteed by characterization.
4
See the Power vs. Throughput Rate section.
Rev. 0 | Page 4 of 28
元器件交易½www.cecb2b.com
AD7911/AD7921
AD7921 SPECIFICATIONS
Temperature range for A Grade from −40°C to +85°C.
V
DD
= 2.35 V to 5.25 V, f
SCLK
= 5 MHz, f
SAMPLE
= 250 kSPS; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
2
Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise (SFDR)
2
Intermodulation Distortion (IMD)
2
Second-Order Terms
Third-Order Term
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
2
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
2
Differential Nonlinearity
2
Offset Error
2
Offset Error Match
2, 3
Gain Error
2
Gain Error Match
2, 3
Total Unadjusted Error (TUE)
2
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
A Grade
1
70
72
71
72.5
−81
−84
−84
−86
10
30
−90
8.5
1.5
12
±1.5
−0.9/+1.5
±1.5
±0.5
±0.5
±2
±0.3
±1
±1.5
0 to V
DD
±0.3
20
0.7 (V
DD
)
2
0.3
0.2 (V
DD
)
0.8
±0.3
±0.3
±0.3
5
V
DD
− 0.2
0.2
±0.3
5
Unit
dB min
dB typ
dB min
dB typ
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB max
V
µA max
pF typ
V min
V min
V max
V max
V max
µA max
µA max
µA max
pF max
V min
V max
µA max
pF max
Straight (natural) binary
2.35 V ≤ V
DD
≤ 2.7 V
2.7 V < V
DD
≤ 5.25 V
V
DD
= 2.35 V
2.35 V < V
DD
≤ 2.7 V
2.7 V < V
DD
≤ 5.25 V
V
IN
= 0 V or V
DD
fa = 100.73 kHz, fb = 90.72 kHz
fa = 100.73 kHz, fb = 90.72 kHz
Test Conditions/Comments
f
IN
= 100 kHz sine wave
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 12 bits
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
, CS Pin
Input Current, I
IN
, DIN Pin
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
See notes at end of table.
I
SOURCE
= 200 µA; V
DD
= 2.35 V to 5.25 V
I
SINK
= 200 µA
Rev. 0 | Page 5 of 28
京公网安备 11010802033920号
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
评论