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Using Verilog-A
Describes how to use Verilog-A in HSPICE and HSPICE RF simulations.
Verilog-A is used to create and use analog behavioral descriptions that
encapsulate high-level behavioral and structural descriptions of systems and
components.
The language allows the behavior of each model, or module, to be described
mathematically in terms of its ports and parameters applied to an instance of
the module. A module can be defined at a level of abstraction appropriate for
the model and analysis, including architectural design, and verification.
Verilog-A supports both a top-down design as well as a bottom-up verification
methodology.
Verilog-A was derived from the IEEE 1364 Verilog Hardware Description
Language (HDL) specification and is intended for describing behavior in analog
systems. The Verilog-A language that HSPICE supports is compliant with
Verilog-AMS Language Reference Manual, Version 2.2,
with limitations listed in
Unsupported Language Features on page 798.
The Verilog-A implementation in HSPICE supports a mixed design of Verilog-A
descriptions and transistor-level SPICE netlists with a simple use model. Most
analysis features available in HSPICE are supported for Verilog-A based
devices, including AC, DC, transient analysis, statistical analysis, and
optimization.
The HSPICE RF supported analysis types are HB, HBOSC, HBAC, HBNOISE,
HBXF, PHASENOISE, SN, SNOSC and ENV.
Note:
Some restrictions for Verilog-A models used with RF simulation algorithms
apply. For example:
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Chapter 31: Using Verilog-A
Getting Started
Verilog-A modules that are time dependent cannot be used for HB or SN
unless the time dependence is periodic with a period that matches the HB
or SN setup.
Verilog-A modules with “internal states” are not guaranteed to work correctly
in HB or SN because the internal state cannot be tracked by the engine, so
HB or SN may think it is converged to a periodic steady-state even though
the internal state may not be in periodic steady state.
Some event-driven constructs in Verilog-A may not be compatible with HB.
These are standard restrictions for Verilog-A in periodic steady-state
analysis and are the same as other RF simulators that use Verilog-A.
These topics are covered in the following sections:
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Getting Started
Introduction to Verilog-A
Simulation with Verilog-A Modules
Loading Verilog-A Devices
Instantiating Verilog-A Devices
Instantiating Primitive Devices inside Verilog-A Modules
Output Simulation Data
Running 32-bit HSPICE Verilog-A on Linux x86_64
Setting Options for the HSPICE Verilog-A Compiler
Unsupported Language Features
Known Limitations
In the context of this chapter, “HSPICE” refers to both HSPICE and HSPICE
RF unless noted otherwise.
Note:
Getting Started
This section explains how to get started using a compact device model written
in Verilog-A in HSPICE.
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Getting Started
*Simple Verilog-A amplifier
.hdl amp.va
vs 1 0 1
rs 1 2 1
x1 2 3 va_amp gain=10
rl 3 0 1
module va_amp(in, out);
parameter real gain = 1.0;
electrical in, out;
analog begin
V(out) <+ gain * V(in);
end
endmodule
Figure 200 HSPICE and Verilog-A
Verilog-A devices use the following conventions:
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Modules are loaded into the simulator with either the
.HDL
netlist command
or the
–hdl
command-line option. The command-line is not supported in
HSPICE RF.
Modules are instantiated in the same manner as HSPICE subcircuits. The
first character for the name of instance should be “X”.
Instance and model parameters can be modified in the same way as other
HSPICE instances.
Module names should not conflict with any HSPICE built-in device keyword
(see
Using Model Cards with Verilog-A Modules on page 779).
If this
happens, HSPICE issues a warning message and ignores the Verilog-A
module definition.
Node voltages and branch currents can be output using conventional output
commands.
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To run an HSPICE Verilog-A simulation, you need to run the “hspice” script,
which is located in the $<installdir>/hspice_2008.03/bin/hspice, regardless of
the platform. For example,
/installed_hspice/hspice_2008.03/bin/hspice
The following example illustrates how a compact device model written in
Verilog-A can be analyzed with HSPICE.
Example: JFET Compact Device Model
HSPICE contains a large number of compact device models coded natively in
the simulator. Verilog-A provides a convenient method to introduce new
compact models. The JFET device model uses a simple expression to relate
the source-drain current to the gate voltage.
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The simplified Verilog-A description of this model is shown.
`include "constants.vams"
`include "disciplines.vams"
module jfet(d, g, s);
parameter real Vto = -2.0 from (-inf:inf); // Threshold voltage
parameter real Beta = 1.0e-4 from [0:inf);// Transconductance
parameter real Lambda = 0.0 from [0:inf); // Channel modulation
electrical d, g, s;
real Id, Vgs, Vds;
analog begin
Vgs = V(g,s);
Vds = V(d,s);
if (Vds <= Vgs-Vto)
Id = Beta*(1+Lambda*Vds)*Vds*(2*(Vgs-Vto)- Vds);
else if (Vgs-Vto < Vds)
Id = Beta*(1+Lambda*Vds)*(Vgs-Vto)*(Vgs-Vto);
I(d,s) <+ Id;
end
endmodule
In this example the module name is
jfet
and the module has three ports,
named
d, g,
and
s.
Three parameters,
Vto, Beta,
and
Lambda,
can be passed
in from the netlist. The electrical behavior is defined between the
analog
begin
and
end
statements. The node voltages across the gate to source and
drain to source is accessed and assigned to the variables
Vgs
and
Vgd.
These
values are used to determine the drain-source current,
Id.
The calculated
current is contributed to the branch from
d
to
s
in the final statement using the
contribution operator,
<+.
This Verilog-A module is loaded into HSPICE with an
.HDL
command in the
netlist. The device is then instantiated using the X prefix for the device name.
The connectivity, module name, and parameter assignments follow the format
of a subcircuit device. The following instantiation line in the netlist is for this
device:
x1 drain gate source jfet Beta=1.1e-4 lambda=0.01
The nodes drain, gate, and source are mapped to the ports d, g, s in the same
order as defined in the module definition. Any parameters in the instantiation
line are passed to the module; otherwise, the default value defined on the
parameter declaration line is used. The parameter declaration allows ranges
and exclusions to be easily defined.
The parameter passed in from the netlist is tested during the simulation and a
run- time error occurs if the parameter is out of the allowed range.
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The device is used in the HSPICE netlist in exactly the same manner that a
built-in device is used. The netlist example shown performs a simple DC-IV
analysis.
Verilog-A version of the SPICE JFET
.hdl jfet.va
.options post=1
VCC Drain 0
VG Gate
0
VS Source 0
3.0
0.5
0.0
X1 Drain Gate Source jfet Vto=-2.0 Beta=1.1e-4 Lambda=0.01
.dc VCC 0.0 4.0 0.01 VG -2.0 0.0 0.5
.print I(VCC)
.end
When the simulation is performed, the program compiles the Verilog-A source
file into a compiled object file. This object file is automatically cached and
subsequent simulations do not require the compile step unless the Verilog-A
source file is modified. After simulation, HSPICE outputs the data in the same
fashion as other devices. In this example the drain-source current is plotted as
a function of Vds and parameterized by Vgs. Figure 201 displays the plot of the
drain-source current for this model.
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