Features 400 MHz ARM926EJS ARM Thumb Processor 32 KBytes Data Cache 32 KBytes Instruction Cache MMU Memories DDR2 Controller 4bank DDR2LPDDR SDRAMLPSDR External Bus Interface supporting 4bank DDR2LPDDR SDRAMLPSDR Static Memories CompactFlash SLC NAND Flash with ECC One 64KByte internal SRAM singlecycle access at system speed or processor speed through TCM interface One 64KByte internal ROM embedding bootstrap routine Peripherals LCD Controller supporting STN and TFT displays up to 128......
Features
•
400 MHz ARM926EJ-S™ ARM
®
Thumb
®
Processor
•
– 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU
Memories
– DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR
– External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static
Memories, CompactFlash, SLC NAND Flash with ECC
– One 64-KByte internal SRAM, single-cycle access at system speed or processor
speed through TCM interface
– One 64-KByte internal ROM, embedding bootstrap routine
Peripherals
– LCD Controller supporting STN and TFT displays up to 1280*860
– ITU-R BT. 601/656 Image Sensor Interface
– USB Device High Speed, USB Host High Speed and USB Host Full Speed with On-
Chip Transceiver
– 10/100 Mbps Ethernet MAC Controller
– Two High Speed Memory Card Hosts (SDIO, SDCard, MMC)
– AC'97 controller
– Two Master/Slave Serial Peripheral Interfaces
– Two Three-channel 16-bit Timer/Counters
– Two Synchronous Serial Controllers (I2S mode)
– Four-channel 16-bit PWM Controller
– Two Two-wire Interfaces
– Four USARTs with ISO7816, IrDA, Manchester and SPI modes
– 8-channel 10-bit ADC with 4-wire Touch Screen support
System
– 133 MHz twelve 32-bit layer AHB Bus Matrix
– 37 DMA Channels
– Boot from NAND Flash, SDCard, DataFlash® or serial DataFlash
– Reset Controller with on-chip Power-on Reset
– Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators
– Internal Low-power 32 kHz RC Oscillator
– One PLL for the system and one 480 MHz PLL optimized for USB High Speed
– Two Programmable External Clock Signals
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock
I/O
– Five 32-bit Parallel Input/Output Controllers
– 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with
Schmitt trigger input
Package
– 324-ball TFBGA, pitch 0.8 mm
•
AT91SAM
ARM-based
Embedded MPU
SAM9G45
•
•
•
6438I–ATARM–16-Dec-11
1. Description
The ARM926EJ-S based SAM9G45 features the frequently demanded combination of user
interface functionality and high data rate connectivity, including LCD Controller, resistive touch-
screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the pro-
cessor running at 400MHz and multiple 100+ Mbps data rate peripherals, the SAM9G45 has the
performance and bandwidth to the network or local storage media to provide an adequate user
experience.
The SAM9G45 supports DDR2 and NAND Flash memory interfaces for program and data stor-
age. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual
external bus interface and distributed memory including a 64-KByte SRAM which can be config-
ured as a tightly coupled memory (TCM) sustains the high bandwidth required by the processor
and the high speed peripherals.
The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory
interface and peripheral I/Os. This feature completely eliminates the need for any external level
shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing.
The SAM9G45 power management controller features efficient clock gating and a battery
backup section minimizing power consumption in active and standby modes.
2
SAM9G45
6438I–ATARM–16-Dec-11
Figure 2-1.
EL
S
BM
NT
RS
T
TD
I
TD
O
TM
TC S
K
RT
CK
JTA
GS
HF
S
HH
DP
SD
A,H
PA
FS
,H
D
HS
MA
VB
DM
G
A
DF
S
DH
DP
SD
/HFS
P/H
DP
H
SD
B,D
LC
PB
FSD
D
LC D0
,D
HS
M/H
D -L
DM
FS
LC
VSY CDD
D
/H
D
N 2
HS
MB
LD
DO
C,L 3
DM
D
T
CD
L
E
C
B
HS
C
N
K
DP
,LC
YN
IS
WR
DC
C
I_
,
C
IS
DO-
LCD
I_
IS
MO
IS PC
I_
I_ K
D11
D
IS HS
I_ Y
IS V N
I_MSYN C
CK C
E
TX
ET
CK
X
-E
E E
R
CR N-E
XC
ER S-E TX
K
E
E X C R
RXER- OL
ET 0-E ERX
X R D
EM
0-ET X3 V
EM
DC
X3
DI
O
M
CI
M 0_D
CI
0 A
_C 0-M
M
DA CI0
C
,M _
M I0_
CI DA
C
I1 CK
1_C 7
_D ,M
CI
DA
A
0-
M 1_C
CI
1_ K
DA
TW
7
T
W D0-
CK TW
0-
D
C TW 1
TS C
RT 0- K1
S CT
SC 0-R S3
K T
RD 0-S S3
X C
TX 0-R K3
D D
0- X3
TX
P
W
D3
M
0-
PW
TC
M
LK
3
TI 0-T
O
A0 CL
-T K2
TI
IO
O
TC B0 A2
L -T
TI K3 IO
O - B
TI A3 TCL 2
O -T K
B3 IO 5
-T A5
IO
B5
N
P
NPCS
C 3
N S
P 2
NPCS
C 1
S S
PC 0
M K
O
M SI
TK ISO
0
T -
F TK
TD 0-T 1
F
RD 0-T 1
0 D
RF -RD1
0
RK -R 1
0- F1
AC
RK1
A 9
C97CK
AC 7F
S
AC97R
97 X
T
SA
TX
DT
R
AD
IG
0X
AD
P
1
AD
XM
2Y
GP
AD
AD3
P
Y
4
TS
-GP
M
AD
AD
V
7
VD RE
DA F
GN NA
DA
N
6438I–ATARM–16-Dec-11
JTAG / Boundary Scan
PIO
HS
Transceiver
HS
Transceiver
2. Block Diagram
TST
In-Circuit Emulator
PA
PB
LCD
8-CH
DMA
ISI
EMAC
HS
USB
DMA
DMA
DMA
DMA
System Controller
PCK0-PCK1
FIQ
IRQ
AIC
ARM926EJ-S
HS EHCI
USB HOST
DMA
SAM9G45 Block Diagram
PIO
DBGU
DRXD
DTXD
DCache
ICache
MMU 32 Kbytes
32 Kbytes
ITCM DTCM Bus Interface
PDC
DDR_A0-DDR_A13
DDR_D0-DDR_D15
DDR_VREF
DDR_DQM[0..1]
DDR_DQS[0..1]
PLLA
I
SRAM
64KB
PLLUTMI PMC
D
DDR2
LPDDR
XIN
XOUT
OSC12M
DDR_CS
DDR_CLK,#DDR_CLK
DDR_CKE
DDR_RAS, DDR_CAS
DDR_WE
DDR_BA0, DDR_BA1
WDT
PIT
RC
4
GPBR
OSC 32K
EBI
RTT
XIN32
XOUT32
SHDN
WKUP
SHDC
RTC
Multi-Layer AHB Matrix
VDDBU
NRST
POR
RSTC
DDR2/
LPDDR/
SDRAM
Controller
VDDCORE
POR
PIOA
ROM
64KB
TRNG
Peripheral
Bridge
Peripheral
DMA
Controller
PIOD
PIOB
PIOC
PIOE
NAND Flash
Controller
ECC
APB
CF
PDC
PDC
SPI0
SPI1
4-CH
PWM
TC0
TC1
TC2
TC3
TC4
TC5
PDC
SSC0
SSC1
PDC
AC97
PDC
8-CH
10Bit ADC
TouchScreen
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15, A18
A16/BA0
A17/BA1
NCS1/SDCS
SDCK, #SDCK, SDCKE
RAS, CAS
SDWE, SDA10
DQM[0..1]
DQS[0..1]
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
NCS0
NANDOE, NANDWE
FIFO
USART0
USART1
USART2
USART3
MCI0/MCI1
SD/SDIO
CE ATA
TWI0
TWI1
Static
Memory
Controller
PIO
D16-D31
NWAIT
DQM[2..3]
A19-A24
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
CFCE1-CFCE2
NCS2
NCS3/NANDCS
SPI0_, SPI1_
SSC0_, SSC1_
SAM9G45
3
3. Signal Description
Table 3-1
gives details on the signal names classified by peripheral.
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