下载中心>资源分类>FPGA/CPLD>其他>bt656 verilog源码

pdf

bt656 verilog源码

1星
2014-09-10
403.99KB
需要1积分
46次下载

下载资源

文档简介
猜您喜欢
用户评论0

标签： bt656 verilog 源码

bt656 verilog源码

Appendix of Verilog Code

/////////////////////////////////////////////////////////////////////////////

// 6.111 FPGA Labkit -- ADV7185 Video Decoder Configuration

// Created:

// Author: Nathan Ickes

/////////////////////////////////////////////////////////////////////////////

// Register 0

/////////////////////////////////////////////////////////////////////////////

`define INPUT_SELECT

4'h0

// 0: CVBS on AIN1 (composite video in)

// 7: Y on AIN2, C on AIN5 (s-video in)

// (These are the only configurations supported by the 6.111 labkit

hardware)

`define INPUT_MODE

4'h0

// 0: Autodetect: NTSC or PAL (BGHID), w/o pedestal

// 1: Autodetect: NTSC or PAL (BGHID), w/pedestal

// 2: Autodetect: NTSC or PAL (N), w/o pedestal

// 3: Autodetect: NTSC or PAL (N), w/pedestal

// 4: NTSC w/o pedestal

// 5: NTSC w/pedestal

// 6: NTSC 4.43 w/o pedestal

// 7: NTSC 4.43 w/pedestal

// 8: PAL BGHID w/o pedestal

// 9: PAL N w/pedestal

// A: PAL M w/o pedestal

// B: PAL M w/pedestal

// C: PAL combination N

// D: PAL combination N w/pedestal

// E-F: [Not valid]

`define ADV7185_REGISTER_0 {`INPUT_MODE, `INPUT_SELECT}

/////////////////////////////////////////////////////////////////////////////

// Register 1

/////////////////////////////////////////////////////////////////////////////

`define

// 0:

// 1:

// 2:

// 3:

`define

// 0:

// 1:

`define

// 0:

VIDEO_QUALITY

Broadcast quality

TV quality

VCR quality

Surveillance quality

SQUARE_PIXEL_IN_MODE

Normal mode

Square pixel mode

DIFFERENTIAL_INPUT

Single-ended inputs

2'h0

1'b0

// 1:

`define

// 0:

// 1:

`define

// 0:

// 1:

`define

// 0:

// 1:

Differential inputs

FOUR_TIMES_SAMPLING

1'b0

Standard sampling rate

4x sampling rate (NTSC only)

BETACAM

1'b0

Standard video input

Betacam video input

AUTOMATIC_STARTUP_ENABLE

1'b1

Change of input triggers reacquire

Change of input does not trigger reacquire

`define ADV7185_REGISTER_1 {`AUTOMATIC_STARTUP_ENABLE, 1'b0, `BETACAM,

`FOUR_TIMES_SAMPLING, `DIFFERENTIAL_INPUT, `SQUARE_PIXEL_IN_MODE,

`VIDEO_QUALITY}

/////////////////////////////////////////////////////////////////////////////

// Register 2

/////////////////////////////////////////////////////////////////////////////

`define

// 0:

// 1:

// 2:

// 3:

// 4:

// 5:

// 6:

// 7:

`define

// 0:

// 1:

// 2:

// 3:

Y_PEAKING_FILTER

Composite = 4.5dB, s-video

Composite = 1.25dB, s-video

Composite = 0.0dB, s-video

Composite = -1.25dB, s-video

Composite = -1.75dB, s-video

Composite = -3.0dB, s-video

CORING

No coring

Truncate if Y < black+8

Truncate if Y < black+16

Truncate if Y < black+32

3'h4

= 9.25dB

= 5.75dB

= 3.3dB

= 0.0dB

= -3.0dB

= -8.0dB

2'h0

`define ADV7185_REGISTER_2 {3'b000, `CORING, `Y_PEAKING_FILTER}

/////////////////////////////////////////////////////////////////////////////

// Register 3

/////////////////////////////////////////////////////////////////////////////

`define INTERFACE_SELECT

2'h0

// 0: Philips-compatible

// 1: Broktree API A-compatible

// 2: Broktree API B-compatible

// 3: [Not valid]

`define OUTPUT_FORMAT

4'h0

// 0: 10-bit @ LLC, 4:2:2 CCIR656

// 1: 20-bit @ LLC, 4:2:2 CCIR656

// 2: 16-bit @ LLC, 4:2:2 CCIR656

// 3: 8-bit @ LLC, 4:2:2 CCIR656

// 4: 12-bit @ LLC, 4:1:1

// 5-F: [Not valid]

// (Note that the 6.111 labkit hardware provides only a 10-bit interface to

// the ADV7185.)

`define TRISTATE_OUTPUT_DRIVERS

1'b0

// 0: Drivers tristated when ~OE is high

// 1: Drivers always tristated

`define VBI_ENABLE

1'b0

// 0: Decode lines during vertical blanking interval

// 1: Decode only active video regions

`define ADV7185_REGISTER_3 {`VBI_ENABLE, `TRISTATE_OUTPUT_DRIVERS,

`OUTPUT_FORMAT, `INTERFACE_SELECT}

/////////////////////////////////////////////////////////////////////////////

// Register 4

/////////////////////////////////////////////////////////////////////////////

`define

// 0:

// 1:

`define

// 0:

// 1:

OUTPUT_DATA_RANGE

1'b0

Output values restricted to CCIR-compliant range

Use full output range

BT656_TYPE

1'b0

BT656-3-compatible

BT656-4-compatible

`define ADV7185_REGISTER_4 {`BT656_TYPE, 3'b000, 3'b110, `OUTPUT_DATA_RANGE}

/////////////////////////////////////////////////////////////////////////////

// Register 5

/////////////////////////////////////////////////////////////////////////////

`define

// 0:

// 1:

`define

// 0:

// 1:

`define

// 0:

// 1:

`define

// 0:

// 1:

GENERAL_PURPOSE_OUTPUTS

4'b0000

GPO_0_1_ENABLE

1'b0

General purpose outputs 0 and 1 tristated

General purpose outputs 0 and 1 enabled

GPO_2_3_ENABLE

1'b0

General purpose outputs 2 and 3 tristated

General purpose outputs 2 and 3 enabled

BLANK_CHROMA_IN_VBI

1'b1

Chroma decoded and output during vertical blanking

Chroma blanked during vertical blanking

HLOCK_ENABLE

1'b0

GPO 0 is a general purpose output

GPO 0 shows HLOCK status

`define ADV7185_REGISTER_5 {`HLOCK_ENABLE, `BLANK_CHROMA_IN_VBI,

`GPO_2_3_ENABLE, `GPO_0_1_ENABLE, `GENERAL_PURPOSE_OUTPUTS}

/////////////////////////////////////////////////////////////////////////////

// Register 7

/////////////////////////////////////////////////////////////////////////////

`define FIFO_FLAG_MARGIN

5'h10

// Sets the locations where FIFO almost-full and almost-empty flags are set

`define FIFO_RESET

1'b0

// 0: Normal operation

// 1: Reset FIFO. This bit is automatically cleared

`define AUTOMATIC_FIFO_RESET

1'b0

// 0: No automatic reset

// 1: FIFO is autmatically reset at the end of each video field

`define FIFO_FLAG_SELF_TIME

1'b1

// 0: FIFO flags are synchronized to CLKIN

// 1: FIFO flags are synchronized to internal 27MHz clock

`define ADV7185_REGISTER_7 {`FIFO_FLAG_SELF_TIME, `AUTOMATIC_FIFO_RESET,

`FIFO_RESET, `FIFO_FLAG_MARGIN}

/////////////////////////////////////////////////////////////////////////////

// Register 8

/////////////////////////////////////////////////////////////////////////////

`define INPUT_CONTRAST_ADJUST

`define ADV7185_REGISTER_8 {`INPUT_CONTRAST_ADJUST}

/////////////////////////////////////////////////////////////////////////////

// Register 9

/////////////////////////////////////////////////////////////////////////////

`define INPUT_SATURATION_ADJUST

`define ADV7185_REGISTER_9 {`INPUT_SATURATION_ADJUST}

/////////////////////////////////////////////////////////////////////////////

// Register A

/////////////////////////////////////////////////////////////////////////////

`define INPUT_BRIGHTNESS_ADJUST

`define ADV7185_REGISTER_A {`INPUT_BRIGHTNESS_ADJUST}

/////////////////////////////////////////////////////////////////////////////

// Register B

/////////////////////////////////////////////////////////////////////////////

`define INPUT_HUE_ADJUST

`define ADV7185_REGISTER_B {`INPUT_HUE_ADJUST}

/////////////////////////////////////////////////////////////////////////////

// Register C

8'h00

8'h8C

8'h80

展开预览

猜您喜欢

上传者

: 电子亮晶晶; 查看他的其他资源

TI 文字链专区

举报人：
被举报人：	电子亮晶晶
举报的资源分：	1
* 类型：
	请您提供公司营业执照和软件相关版权到service@eeworld.com.cn
* 详细原因：

bt656 verilog源码

文档简介

评论

汽车 模拟

汽车模拟