The DS90CF563 transmitter converts 21 bits of CMOS/TTLdata into three LVDS (Low Voltage Differential Signaling)data streams. A phase-locked transmit clock is transmitted inparallel with the data streams over a fourth LVDS link. Everycycle of the transmit clock 21 bits of input data are sampledand transmitted. The DS90CF564 receiver converts theLVDS data streams back into 21 bits of CMOS/TTL data. Ata transmit clock frequency of 65 MHz, 18 bits of RGB dataand 3 bits of LCD timing and control data (FPLINE,FPFRAME, DRDY) are transmitted at a rate of 455 Mbps perLVDS data channel. Using a 65 MHz clock, the data throughputis 171 Mbytes per second. These devices are offeredwith falling edge data strobes for convenient interface with avariety of graphics and LCD panel controllers.
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