The Infineon TriCore provides an Interrupt System on a high safety standard. Thisdocument contains instructions on how to configure the TriCore registers to generate a timer interrupt based on an overflow trigger from a 32-bit count register.1 Overview32 The basic steps to an Interrupt 42.1 The general settings 42.2 Service request specific Individual settings42.3 Enabling the GPTU by setting the Clock Register CLC 62.4 Initialization of the Timer Registers 62.5 Software example: Timer Interrupt 93 Appendix 123.1 xxSRC – Source xx Service Request Control Register..123.2 ICR – Interrupt Control Register...133.3 T012RUN – Timer Run Control Register..143.4 T01IRS – Input and Reload Source Selection Register 163.5 T0DCBA – Timer T0 Count Register..173.6 T0RDCBA – Timer T0 Reload Register ...173.7 T01OTS – Output, Trigger and Service Request Selection Register 183.8 GTSRSEL – GPT Service Request Source Selection Register ..193.9 CLC – Clock Control Register 20
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