Introduction
Overview
The Device Under Test (D.U.T.)
The Test Bench
Instantiations
Figure 1- DUT Instantiation
Reg and Wire Declarations
Figure 2 – Reg and Wire Declarations
Initial and Always Blocks
Figure 3 – An Initial Block Example
Figure 4 – An Always Block Example
Initialization
Delays
Clocks and Resets
Assign Statements.
Figure 5- An Assign Example
Printing during Simulations
$display
Figure 6- $display Example
$monitor
Figure 7- Using $monitor
Tasks
Figure 8- An Example of a Task – load_count
Count16 Simulation Example
Table 1- Simulation Steps
Figure 9 – The Transcript Window for the Count16 Simulation
Figure 10 – The Simulation Waveform Window for the Count16 Simulation..
Gate Level Simulations
Appendix A- The count16.v Verilog Source File
Appendix B- The cnt16_tb.v Verilog Test Bench Source File
Reference Materials
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