FPGA控制AD9957的操作，调试过，VERILOG HDL编写

文件列表: 

    modulator

    .........\\\\ad9957_dac.v

    .........\\\\ad9957_dac_summary.html

    .........\\\\ad9957_qudc.v

    .........\\\\ad9957_qudc_summary.html

    .........\\\\ad9957_single.stx

    .........\\\\ad9957_single.syr

    .........\\\\ad9957_single.v

    .........\\\\ad9957_single_cs.blc

    .........\\\\ad9957_single_cs.cdc

    .........\\\\ad9957_single_sim.v

    .........\\\\ad9957_single_summary.html

    .........\\\\config_ad9957.v

    .........\\\\data.coe

    .........\\\\dcmclk.v

    .........\\\\dcmclk.xaw

    .........\\\\dcmclk_arwz.ucf

    .........\\\\modulator.bgn

    .........\\\\modulator.bit

    .........\\\\modulator.bld

    .........\\\\modulator.cmd_log

    .........\\\\modulator.drc

    .........\\\\modulator.ipf

    .........\\\\modulator.ipf_ISE_Backup

    .........\\\\modulator.ise

    .........\\\\modulator.ise_ISE_Backup

    .........\\\\modulator.ncd

    .........\\\\modulator.ngc

    .........\\\\modulator.ngd

    .........\\\\modulator.ngr

    .........\\\\modulator.pad

    .........\\\\modulator.par

    .........\\\\modulator.pcf

    .........\\\\modulator.syr

    .........\\\\modulator.twr

    .........\\\\modulator.twx

    .........\\\\modulator.ucf

    .........\\\\modulator.unroutes

    .........\\\\modulator.ut

    .........\\\\modulator.v

    .........\\\\modulator.xst

    .........\\\\modulator_last_par.ncd

    .........\\\\modulator_map.mrp

    .........\\\\modulator_map.ncd

    .........\\\\modulator_map.ngm

    .........\\\\modulator_pad.csv

    .........\\\\modulator_pad.txt

    .........\\\\modulator_sim.v

    .........\\\\modulator_sim_v.fdo

    .........\\\\modulator_sim_v.ndo

    .........\\\\modulator_sim_v.udo

    .........\\\\modulator_summary.html

    .........\\\\netgen

    .........\\\\......\\\\translate

    .........\\\\......\\\\.........\\\\modulator_translate.nlf

    .........\\\\......\\\\.........\\\\modulator_translate.v

    .........\\\\rcosflt_lookup.stx

    .........\\\\rcosflt_lookup.v

    .........\\\\rcosflt_lookup_sim.v

    .........\\\\rcosflt_lookup_sim_v.fdo

    .........\\\\rcosflt_lookup_sim_v.udo

    .........\\\\rcosflt_lookup_summary.html

    .........\\\\serial.stx

    .........\\\\serial.v

    .........\\\\serial_rd.stx

    .........\\\\serial_rd.v

    .........\\\\serial_rd_sim.v

    .........\\\\serial_rw.v

    .........\\\\serial_sim.v

    .........\\\\serial_sim_v.fdo

    .........\\\\serial_sim_v.udo

    .........\\\\serial_wr.stx

    .........\\\\serial_wr.v

    .........\\\\serial_wr_sim.v

    .........\\\\sram_ctrl.asy

    .........\\\\sram_ctrl.edn

    .........\\\\sram_ctrl.mif

    .........\\\\sram_ctrl.sym

    .........\\\\sram_ctrl.v

    .........\\\\sram_ctrl.veo

    .........\\\\sram_ctrl.vhd

    .........\\\\sram_ctrl.vho

    .........\\\\sram_ctrl.xco

    .........\\\\sram_ctrl_flist.txt

    .........\\\\sram_ctrl_readme.txt

    .........\\\\tcl_stacktrace.txt

    .........\\\\templates

    .........\\\\.........\\\\coregen.xml

    .........\\\\transcript

    .........\\\\Untitled.mcs

    .........\\\\Untitled.prm

    .........\\\\vsim.wlf

    .........\\\\work

    .........\\\\....\\\\ad9957_single

    .........\\\\....\\\\.............\\\\verilog.asm

    .........\\\\....\\\\.............\\\\_primary.dat

    .........\\\\....\\\\.............\\\\_primary.vhd

    .........\\\\....\\\\dcmclk

    ...  ...