a
FEATURES
Fast 16-Bit ADC with 200 kSPS Throughput
Four Single-Ended Analog Input Channels
Single +5 V Supply Operation
Input Ranges: 0 V to +4 V, 0 V to +5 V and 10 V
120 mW Max Power Dissipation
Power-Down Mode 50 W
Choice of External or Internal 2.5 V Reference
On-Chip Clock
Power-Down Mode
V1A
V1B
4-Channel, 16-Bit, 200 kSPS
Data Acquisition System
AD974
FUNCTIONAL BLOCK DIAGRAM
PWRD
BIP
CAP
REF
V
DIG
V
ANA
REF
BUFF
RESISTIVE
NETWORK
2.5V
REFERENCE
AD974
EXT/INT
SWITCHED 16
CAP ADC
DATACLK
SERIAL
INTERFACE
DATA
R/C
CS
CLOCK
SYNC
V2A
V2B
RESISTIVE
NETWORK
4 TO 1
MUX
+
LATCH
V3A
V3B
RESISTIVE
NETWORK
V4A
V4B
RESISTIVE
NETWORK
EN
CONTROL LOGIC
&
CALIBRATION CIRCUITRY
GENERAL DESCRIPTION
The AD974 is a four-channel, data acquisition system with a
serial interface. The part contains an input multiplexer, a high-
speed 16-bit sampling ADC and a +2.5 V reference. All of this
operates from a single +5 V power supply that also has a power-
down mode. The part will accommodate 0 V to +4 V, 0 V to
+5 V or
±
10 V analog input ranges.
The interface is designed for an efficient transfer of data while
requiring a low number of interconnects.
The AD974 is comprehensively tested for ac parameters such as
SNR and THD, as well as the more traditional parameters of
offset, gain and linearity.
The AD974 is fabricated on Analog Devices’ BiCMOS process,
which has high performance bipolar devices along with CMOS
transistors.
The AD974 is available in 28-lead DIP, SOIC and SSOP
packages.
AGND1 AGND2
A0 A1
WR1 WR2
BUSY
DGND
PRODUCT HIGHLIGHTS
1. The AD974 is a complete data acquisition system combining
a four-channel multiplexer, a 16-bit sampling ADC and a
+2.5 V reference on a single chip.
2. The part operates from a single +5 V supply and also has a
power-down feature.
3. Interfacing to the AD974 is simple with a low number of
interconnect signals.
4. The AD974 is comprehensively specified for ac parameters
such as SNR and THD, as well as dc parameters such as
linearity and offset and gain errors.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD974–SPECIFICATIONS
(–40 C to +85 C, f = 200 kHz, V
S
DIG
= V
ANA
= +5 V, unless otherwise noted)
Min
16
B Grade
Typ Max
Units
Bits
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Impedance
Sampling Capacitance
THROUGHPUT SPEED
Complete Cycle
(Acquire and Convert)
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
2
Full-Scale Error
3
Full-Scale Error Drift
Full-Scale Error
Full-Scale Error Drift
Bipolar Zero Error
Bipolar Zero Error Drift
Unipolar Zero Error
Unipolar Zero Error Drift
Channel-to-Channel Matching
Recovery to Rated Accuracy
After Power-Down
4
Power Supply Sensitivity
V
ANA
= V
DIG
= V
D
AC ACCURACY
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Channel-to-Channel Isolation
Full Power Bandwidth
6
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Transient Response
Overvoltage Recovery
7
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
Conditions
Min
16
A Grade
Typ
Max
Channel On or Off
±
10 V, 0 V to +4 V, 0 V to +5 V (See Table I)
(See Table I)
40
40
pF
5
200
±
3
+3
1.0
Internal Reference
Internal Reference
Ext. REF = +2.5 V
Ext. REF = +2.5 V
Bipolar Range
Bipolar Range
Unipolar Ranges
Unipolar Ranges
2.2
µF
to CAP
V
D
= 5 V
±
5%
f
IN
= 20 kHz
f
IN
= 20 kHz
f
IN
= 20 kHz
–60 dB Input
f
IN
= 20 kHz
f
IN
= 20 kHz
90
–90
83
27
83
–110
1
2.7
40
Full-Scale Step
150
2.48
2.3
Ext. REF = +2.5 V
2.5
1
2.5
2.52
2.7
100
2.48
2.3
1
150
2.5
1
2.5
–100
85
–110
1
2.7
40
85
28
±
7
±
2
±
2
±
2
1
±
8
96
±
0.5
±
0.5
±
10
±
10
±
0.1
200
5
µs
kHz
LSB
1
LSB
Bits
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
mV
ppm/°C
% FSR
ms
–2
15
–1
16
1.0
±
7
±
2
±
2
±
2
1
±
2.0
+1.75
±
0.25
±
0.25
±
10
±
10
±
0.05
±
8
LSB
dB
5
dB
dB
dB
dB
dB
MHz
MHz
ns
µs
ns
V
µA
V
µA
–96
–100
1
2.52
2.7
100
–0.3
+2.0
+0.8
V
DIG
+ 0.3
±
10
±
10
–0.3
+2.0
+0.8
V
DIG
+ 0.3
±
10
±
10
V
V
µA
µA
–2–
REV. A
AD974
Parameter
DIGITAL OUTPUTS
Data Format
Data Coding
V
OL
V
OH
Output Capacitance
Leakage Current
POWER SUPPLIES
Specified Performance
V
DIG
V
ANA
I
DIG
I
ANA
Power Dissipation
PWRD LOW
PWRD HIGH
TEMPERATURE RANGE
Specified Performance
T
MIN
to T
MAX
Conditions
Min
A Grade
Typ
Max
B Grade
Min Typ Max
Units
Serial 16 Bits
Straight Binary
+0.4
+4
15
±
5
I
SINK
= 1.6 mA
I
SOURCE
= 500
µA
High-Z State
High-Z State
V
OUT
= 0 V to V
DIG
+0.4
15
±
5
+4
V
V
pF
µA
+4.75
+4.75
+5
+5
4.5
14
50
+5.25
+5.25
+4.75 +5
+4.75 +5
4.5
14
50
+5.25
+5.25
V
V
mA
mA
mW
µW
°C
120
120
–40
+85
–40
+85
NOTES
1
LSB means Least Significant Bit. With a
±10
V input, one LSB is 305
µV.
2
Typical rms noise at worst case transitions and temperatures.
3
Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage, and includes the effect
of offset error. For bipolar input, the Full-Scale Error is the worst case of either the –Full-Scale or +Full-Scale code transition voltage errors. For unipolar input
ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.
4
External 2.5 V reference connected to REF.
5
All specifications in dB are referred to a full-scale
±10
V input.
6
Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB, or 10 bits of accuracy.
7
Recovers to specified performance after a 2
×
FS input overvoltage.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(f = 200 kHz, V
S
DIG
= V
ANA
= +5 V, –40 C to +85 C)
Min
50
100
4.0
50
40
3.8
1.0
5
220
220
50
20
66
20
30
20
10
15
25
10
3.5
5
10
10
50
Typ
Max
Units
ns
ns
µs
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
ns
ns
Parameter
Convert Pulsewidth
R/C,
CS
to
BUSY
Delay
BUSY
LOW Time
BUSY
Delay after End of Conversion
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
R/C Low to DATACLK Delay
DATACLK Period
DATA Valid Setup Time
DATA Valid Hold Time
EXT. DATACLK Period
EXT. DATACLK HIGH
EXT. DATACLK LOW
R/C,
CS
to EXT. DATACLK Setup Time
R/C to
CS
Setup Time
EXT. DATACLK to SYNC Delay
EXT. DATACLK to DATA Valid Delay
CS
to EXT. DATACLK Rising Edge Delay
Previous DATA Valid after
CS,
R/C Low
BUSY
to EXT. DATACLK Setup Time
Final EXT. DATACLK to
BUSY
Rising Edge
A0, A1 to
WR1, WR2
Setup Time
A0, A1 to
WR1, WR2
Hold Time
WR1, WR2
Pulsewidth
Specifications subject to change without notic e.
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
6
+ t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
4.0
t
12
+ 5
66
66
1.7
REV. A
–3–
AD974
ABSOLUTE MAXIMUM RATINGS
1
PIN CONFIGURATION
SOIC, DIP AND SSOP
Analog Inputs
VxA, VxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
CAP . . . . . . . . . . . . . . . . +V
ANA
+ 0.3 V to AGND2 – 0.3 V
REF . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2,
Momentary Short to V
ANA
Ground Voltage Differences
DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . .
±
0.3 V
Supply Voltages
V
ANA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
V
DIG
to V
ANA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±7
V
V
DIG
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.3 V to V
DIG
+ 0.3 V
Internal Power Dissipation
2
PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature Range N, R . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
28-Lead PDIP:
θ
JA
= 100°C/W,
θ
JC
= 31°C/W
28-Lead SOIC:
θ
JA
= 75°C/W,
θ
JC
= 24°C/W
28-Lead SSOP:
θ
JA
= 109°C/W,
θ
JC
= 39°C/W
AGND1
1
V3A
2
V3B
3
V4A
4
V4B
5
BIP
6
CAP
7
28
V2B
27
V2A
26
V1B
25
V1A
24
V
ANA
AD974
23
A0
TOP VIEW
22
A1
REF
8
(Not to Scale)
21
BUSY
20
CS
19
WR1
18
WR2
17
DATA
16
DATACLK
15
SYNC
AGND2
9
R/C
10
V
DIG 11
PWRD
12
EXT/INT
13
DGND
14
1.6mA
I
OL
TO OUTPUT
PIN
+1.4V
C
L
100pF
500 A
I
OH
Figure 1. Load Circuit for Digital Interface Timing
ORDERING GUIDE
Model
AD974AN
AD974BN
AD974AR
AD974BR
AD974ARS
AD974BRS
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Max INL
±
3.0 LSB
±
2.0 LSB
±
3.0 LSB
±
2.0 LSB
±
3.0 LSB
±
2.0 LSB
Min S/(N+D)
83 dB
85 dB
83 dB
85 dB
83 dB
85 dB
Package
Description
28-Lead Plastic DIP
28-Lead Plastic DIP
28-Lead SOIC
28-Lead SOIC
28-Lead SSOP
28-Lead SSOP
Package
Options
N-28B
N-28B
R-28
R-28
RS-28
RS-28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD974 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD974
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2–5, 25–28
6
7
8
Mnemonic
AGND1
VxA, VxB
BIP
CAP
REF
Description
Analog Ground. Used as the ground reference point for the REF pin.
Analog Input. Refer to Table I for input range configuration.
Bipolar Offset. Connect VxA inputs to provide Bipolar input range.
Reference Buffer Output. Connect a 2.2
µF
tantalum capacitor between CAP and Analog
Ground.
Reference Input/Output. The internal +2.5 V reference is available at this pin. Alternatively an
external reference can be used to override the internal reference. In either case, connect a 2.2
µF
tantalum capacitor between REF and Analog Ground.
Analog Ground.
Read/Convert Input. Used to control the conversion and read modes. With
CS
LOW, a falling
edge on R/C holds the analog input signal internally and starts a conversion; a rising edge enables
the transmission of the conversion result.
Digital Power Supply. Nominally +5 V.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited. The conversion result from the previous conversion is stored in the onboard shift
register.
Digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW,
after initiating a conversion, 16 DATACLK pulses transmit the previous conversion result as
shown in Figure 3. With EXT/INT set to a Logic HIGH, output data is synchronized to an
external clock signal connected to the DATACLK input. Data is output as indicated in Figure 4
through Figure 9.
Digital Ground.
Digital output frame synchronization for use with an external data clock (EXT/INT = Logic
HIGH). When a read sequence is initiated, a pulse one DATACLK period wide is output
synchronous to the external data clock.
Serial data clock input or output, dependent upon the logic state of the EXT/INT pin. When
using the internal data clock (EXT/INT = Logic LOW), a conversion start sequence will initiate
transmission of 16 DATACLK periods. Output data is synchronous to this clock and is valid on
both its rising and falling edges (Figure 3). When using an external data clock (EXT/INT = Logic
HIGH), the
CS
and R/C signals control how conversion data is accessed.
The serial data output is synchronized to DATACLK. Conversion results are stored in an on-
chip register. The AD974 provides the conversion result, MSB first, from its internal shift regis-
ter. When using the internal data clock (EXT/INT = Logic LOW), DATA is valid on both the
rising and falling edges of DATACLK. Using an external data clock (EXT/INT = Logic HIGH)
allows previous conversion data to be accessed during a conversion (Figures 5, 7 and 9) or the
conversion result can be accessed after the completion of a conversion (Figures 4, 6 and 8).
Multiplexer Write Inputs. These inputs are internally ORed to generate the mux latch inputs.
The latch is transparent when
WR1
and
WR2
are tied low.
Chip Select Input. With R/C LOW, a falling edge on
CS
will initiate a conversion. With R/C
HIGH, a falling edge on
CS
will enable the serial data output sequence.
Busy Output. Goes LOW when a conversion is started, and remains LOW until the conversion is
completed and the data is latched into the on-chip shift register.
Address multiplexer inputs latched with the
WR1, WR2
inputs.
A1
0
0
1
1
A0
0
1
0
1
Data Available from Channel
AIN 1
AIN 2
AIN 3
AIN 4
9
10
AGND2
R/C
11
12
V
DIG
PWRD
13
EXT/INT
14
15
DGND
SYNC
16
DATACLK
17
DATA
18, 19
20
21
22, 23
WR1, WR2
CS
BUSY
A1, A0
24
V
ANA
Analog Power Supply. Nominally +5 V.
REV. A
–5–
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