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tlc5615的数据手册

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标签： tlc5615

tlc5615

手册

手册

tlc数据手册  10位串行dac芯片，易于与单片机等微处理器接口。

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TLC5615C TLC5615I SLAS142EOCTOBER 1996REVISED JUNE 2007 10BIT DIGITALTOANALOG CONVERTERS FEATURES 10Bit CMOS Voltage Output DAC in an 8Terminal Package 5V Single Supply Operation 3Wire Serial Interface HighImpedance Reference Inputs Voltage Output Range 2 Times the Reference Input Voltage Internal PowerOn Reset Low Power Consumption 175mW Max Update Rate of 121MHz Settling Time to 05LSB 125m s Typ Monotonic Over Temperature PinCompatible With the Maxim MAX515 APPLICATIONS BatteryPowe......

TLC5615C, TLC5615I
www.ti.com
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
10-BIT DIGITAL-TO-ANALOG CONVERTERS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10-Bit CMOS Voltage Output DAC in an
8-Terminal Package
5V Single Supply Operation
3-Wire Serial Interface
High-Impedance Reference Inputs
Voltage Output Range: 2 Times the Reference
Input Voltage
Internal Power-On Reset
Low Power Consumption: 1.75mW Max
Update Rate of 1.21MHz
Settling Time to 0.5LSB: 12.5µs Typ
Monotonic Over Temperature
Pin-Compatible With the Maxim MAX515
DESCRIPTION
The TLC5615 is a 10-bit voltage output
digital-to-analog converter (DAC) with a buffered
reference input (high impedance). The DAC has an
output voltage range that is two times the reference
voltage, and the DAC is monotonic. The device is
simple to use, running from a single supply of 5V. A
power-on-reset function is incorporated to ensure
repeatable start-up conditions.
Digital control of the TLC5615 is over a three-wire
serial bus that is CMOS compatible and easily
interfaced to industry standard microprocessor and
microcontroller devices. The device receives a 16-bit
data word to produce the analog output. The digital
inputs feature Schmitt triggers for high noise
immunity. Digital communication protocols include
the SPI™, QSPI™, and Microwire™ standards.
The 8-terminal small-outline D package allows digital
control of analog functions in space-critical
applications. The TLC5615C is characterized for
operation from 0°C to +70°C. The TLC5615I is
characterized for operation from –40°C to +85°C.
D, P, OR DGK PACKAGE
(TOP VIEW)
APPLICATIONS
Battery-Powered Test Instruments
Digital Offset and Gain Adjustment
Battery Operated/Remote Industrial Controls
Machine and Motion Control Devices
Cellular Telephones
DIN
SCLK
CS
DOUT
1
2
3
4
8
7
6
5
V
DD
OUT
REFIN
AGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2007, Texas Instruments Incorporated
TLC5615C, TLC5615I
www.ti.com
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
FUNCTIONAL BLOCK DIAGRAM
_
REFIN
+
DAC
+
_ 2
OUT
(Voltage Output)
R
AGND
Power-ON
Reset
R
10-Bit DAC Register
Control
Logic
2
0s
(LSB)
(MSB)
4
Dummy
Bits
DOUT
CS
SCLK
DIN
10 Data Bits
16-Bit Shift Register
Terminal Functions
TERMINAL
NAME
DIN
SCLK
CS
DOUT
AGND
REFIN
OUT
V
DD
NO.
1
2
3
4
5
6
7
8
I
O
I/O
I
I
I
O
Serial data input
Serial clock input
Chip select, active low
Serial data output for daisy chaining
Analog ground
Reference input
DAC analog voltage output
Positive power supply
DESCRIPTION
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at
www.ti.com.
2
Submit Documentation Feedback
TLC5615C, TLC5615I
www.ti.com
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage (V
DD
to AGND)
Digital input voltage range to AGND
Reference input voltage range to AGND
Output voltage at OUT from external source
Continuous current at any terminal
Operating free-air temperature range, T
A
Storage temperature range, T
stg
Lead temperature 1,6mm (1/16 inch) from case for 10 seconds
(1)
TLC5615C
TLC5615I
7V
–0.3V to V
DD
+ 0.3V
–0.3V to V
DD
+ 0.3V
V
DD
+ 0.3V
±20mA
0°C to +70°C
–40°C to +85°C
–65°C to +150°C
+260°C
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, V
DD
High-level digital input voltage, V
IH
Low-level digital input voltage, V
IL
Reference voltage, V
ref
to REFIN terminal
Load resistance, R
L
Operating free-air temperature, T
A
TLC5615C
TLC5615I
2
2
0
40
70
85
2.048
4.5
2.4
0.8
V
DD
–2
NOM
5
MAX
5.5
UNIT
V
V
V
V
kΩ
°C
°C
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, V
DD
= 5V
±
5%, V
ref
= 2.048V (unless otherwise noted)
STATIC DAC SPECIFICATIONS
PARAMETER
Resolution
Integral nonlinearity, end point adjusted (INL)
Differential nonlinearity (DNL)
E
ZS
E
G
Zero-scale error (offset error at zero scale)
Zero-scale-error temperature coefficient
Gain error
Gain-error temperature coefficient
PSRR Power-supply rejection ratio
Analog full scale output
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Zero scale
Gain
V
ref
= 2.048V,
V
ref
= 2.048V,
V
ref
= 2.048V,
V
ref
= 2.048V,
V
ref
= 2.048V,
V
ref
= 2.048V,
See
(7) (8)
TEST CONDITIONS
See
See
See
See
See
See
(1)
(2)
(3)
(4)
(5)
(6)
MIN
10
TYP
MAX
±1
UNIT
bits
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
dB
±0.1
3
±0.5
±3
±3
1
80
80
2V
ref
(1023/1024)
R
L
= 100kΩ
V
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from
the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). Tested from code 3 to code 1024.
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1LSB
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)
as a change in the digital input code. Tested from code 3 to code 1024.
Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).
Zero-scale-error temperature coefficient is given by: E
ZS
TC = [E
ZS
(T
max
) – E
ZS
(T
min
)]/V
ref
×
10
6
/(T
max
– T
min
).
Gain error is the deviation from the ideal output (V
ref
– 1LSB) with an output load of 10kΩ excluding the effects of the zero-scale error.
Gain temperature coefficient is given by: E
G
TC = [E
G
(T
max
) – E
G
(T
min
)]/V
ref
×
10
6
/(T
max
– T
min
).
Zero-scale-error rejection ratio (EZS-RR) is measured by varying the V
DD
from 4.5V to 5.5V dc and measuring the proportion of this
signal imposed on the zero-code output voltage.
Gain-error rejection ratio (EG-RR) is measured by varying the V
DD
from 4.5V to 5.5V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero-scale change.
Submit Documentation Feedback
3
TLC5615C, TLC5615I
www.ti.com
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
VOLTAGE OUTPUT (OUT)
PARAMETER
V
O
I
OSC
V
OL(low)
V
OH(high)
V
I
r
i
C
i
V
IH
V
IL
I
IH
I
IL
C
i
V
OH
V
OL
V
DD
Voltage output range
Output load regulation accuracy
Output short circuit current
Output voltage, low-level
Output voltage, high-level
Input voltage
Input resistance
Input capacitance
High-level digital input voltage
Low-level digital input voltage
High-level digital input current
Low-level digital input current
Input capacitance
Output voltage, high-level
Output voltage, low-level
Supply voltage
V
DD
= 5.5V, No load,
All inputs = 0V or V
DD
V
DD
= 5.5V, No load,
All inputs = 0V or V
DD
V
ref
= 0
V
ref
= 2.048V
I
O
= –2mA
I
O
= 2mA
4.5
5
150
230
V
DD
–1
0.4
5.5
250
350
V
I
= V
DD
V
I
= 0
8
2.4
0.8
±1
±1
R
L
= 10kΩ
V
O(OUT)
= 2V,
OUT to V
DD
or AGND
I
O(OUT)
≤
5mA
I
O(OUT)
≤–
5mA
4.75
0
10
5
V
DD
–2
R
L
= 2kΩ
20
0.25
TEST CONDITIONS
MIN
0
TYP
MAX
V
DD
–0.4
0.5
UNIT
V
LSB
mA
V
V
V
MΩ
pF
V
V
µA
µA
pF
V
V
V
µA
µA
REFERENCE INPUT (REFIN)
DIGITAL INPUTS (DIN, SCLK, CS)
DIGITAL OUTPUT (DOUT)
POWER SUPPLY
I
DD
Power supply current
ANALOG OUTPUT DYNAMIC PERFORMANCE
Signal-to-noise + distortion, S/(N+D)
(1)
V
ref
= 1V
PP
at 1kHz + 2.048Vdc,
code = 11 1111 1111
(1)
60
dB
The limiting frequency value at 1V
PP
is determined by the output-amplifier slew rate.
DIGITAL INPUT TIMING REQUIREMENTS (See
Figure 1)
PARAMETER
t
su(DS)
t
h(DH)
t
su(CSS)
t
su(CS1)
t
h(CSH0)
t
h(CSH1)
t
w(CS)
t
w(CL)
t
w(CH)
Setup time, DIN before SCLK high
Hold time, DIN valid after SCLK high
Setup time, CS low to SCLK high
Setup time, CS high to SCLK high
Hold time, SCLK low to CS low
Hold time, SCLK low to CS high
Pulse duration, minimum chip select pulse width high
Pulse duration, SCLK low
Pulse duration, SCLK high
MIN
45
0
1
50
1
0
20
25
25
NOM
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT SWITCHING CHARACTERISTICS
PARAMETER
t
pd(DOUT)
Propagation delay time, DOUT
C
L
= 50pF
TEST CONDITIONS
MIN NOM MAX
50
UNIT
ns
4
Submit Documentation Feedback
TLC5615C, TLC5615I
www.ti.com
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
OPERATING CHARACTERISTICS
over recommended operating free-air temperature range, V
DD
= 5V
±5%,
V
ref
= 2.048V (unless otherwise noted)
PARAMETER
ANALOG OUTPUT DYNAMIC PERFORMANCE
SR
t
s
Output slew rate
Output settling time
Glitch energy
REFERENCE INPUT (REFIN)
Reference feedthrough
Reference input
bandwidth (f–3dB)
(1)
(2)
REFIN = 1V
PP
at 1kHz + 2.048Vdc
REFIN = 0.2V
PP
+ 2.048Vdc
(2)
TEST CONDITIONS
C
L
= 100pF,
T
A
= +25°C
To 0.5LSB,
R
L
= 10kΩ,
DIN = All 0s to all 1s
MIN
TYP
MAX
UNIT
R
L
= 10kΩ,
C
L
= 100pF,
(1)
0.3
0.5
12.5
5
–80
30
V/µs
µs
nV-s
dB
kHz
Settling time is the time for the output signal to remain within
±0.5LSB
of the final measured value for a digital input code change of 000
hex to 3FF hex or 3FF hex to 000 hex.
Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
ref
input = 2.048Vdc + 1V
pp
at 1kHz.
PARAMETER MEASUREMENT INFORMATION
CS
t
w(CH)
t
w(CL)
t
h(CSH1)
SCLK
See Note A
t
su(DS)
t
h(DH)
DIN
t
pd(DOUT)
MSB
DOUT
Previous LSB
See Note B
NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.
B. Data input from preceeding conversion cycle.
C. Sixteenth SCLK falling edge
Figure 1. Timing Diagram
Submit Documentation Feedback
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
su(CS1)
See Note C
See Note A
LSB
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
t
h(CSH0)
t
su(CSS)
t
w(CS)
5
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