datasheet

电子技术资料下载

热搜关键词： 电路基础ADC数字信号处理封装库PLC

下载中心>资源分类>电子电路>模拟及混合电路>AD9854英文资料
pdf

AD9854英文资料

  • 1星
  • 2015-04-06
  • 435.55KB
  • 需要1积分
  • 1次下载
下载资源
标签： AD9854

AD9854

ad9854英文pdf资料。。

a
FEATURES
300 MHz Internal Clock Rate
Integrated 12-Bit Output DAC
Ultrahigh-Speed, 3 ps RMS Jitter Comparator
Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz
( 1 MHz) A
OUT
4 to 20 Programmable Reference Clock Multiplier
Dual 48-Bit Programmable Frequency Registers
Dual 14-Bit Programmable Phase Offset Registers
12-Bit Amplitude Modulation and Programmable
Shaped On/Off Keying Function
Single Pin FSK and PSK Data Interface
Linear or Nonlinear FM Chirp Functions with Single
Pin Frequency “Hold” Function
Frequency-Ramped FSK
<25 ps RMS Total Jitter in Clock Generator Mode
Automatic Bidirectional Frequency Sweeping
SIN(x)/x Correction
Simplified Control Interface
10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible or
100 MHz Parallel 8-Bit Programming
CMOS 300 MHz Quadrature
Complete-DDS
AD9854
3.3 V Single Supply
Multiple Power-Down Functions
Single-Ended or Differential Input Reference Clock
Small 80-Lead LQFP Packaging
APPLICATIONS
Agile, Quadrature L.O. Frequency Synthesis
Programmable Clock Generator
FM Chirp Source for Radar and Scanning Systems
Test and Measurement Equipment
Commercial and Amateur RF Exciter
GENERAL DESCRIPTION
The AD9854 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with two internal
high-speed, high-performance quadrature D/A converters and a
comparator to form a digitally-programmable I and Q synthesizer
function. When referenced to an accurate clock source, the
AD9854 generates highly stable, frequency-phase-amplitude-
programmable sine and cosine outputs that can be used as an
agile L.O. in communications, radar, and many other applications.
The AD9854’s innovative high-speed DDS core provides 48-bit
frequency resolution (1 microHertz tuning steps). Phase trunca-
tion to 17 bits assures excellent SFDR. The AD9854’s circuit
(continued
on page 14)
FUNCTIONAL BLOCK DIAGRAM
DAC R
SET
300MHz
DIFF/SINGLE
SELECT
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
DDS
SINE-TO-AMPLITUDE
CONVERTER
INV.
SINC
FILTER
DIGITAL
MULTIPLIERS
I
12-BIT "I"
DAC
ANALOG OUT
REFERENCE
CLOCK IN
4 –20
REF CLK
MULTI-
PLEXER
SYSTEM
CLOCK
Q
PHASE/OFFSET
MODULATION
INV.
SINC
FILTER
RAMP-UP/-DOWN
CLOCK/LOGIC
AND
MULTIPLEXER
MUX
12-BIT
"Q" OR
CONTROL DAC
ANALOG OUT
FSK/BPSK/HOLD
DATA IN
FREQUENCY TUNING WORD/PHASE WORD
MULTIPLEXER AND RAMP START STOP LOGIC
48-BIT
FREQUENCY
TUNING WORD
14-BIT PHASE
OFFSET/
MODULATION
SHAPED
ON/OFF KEYING
12-BIT CONTROL
DAC DATA
ANALOG IN
AD9854
12-BIT
AM
MOD
BIDIRECTIONAL
I/O UPDATE
READ
WRITE
PROGRAMMING REGISTERS
I/O PORT BUFFERS
PROGRAMMABLE RATE
AND UPDATE CLOCKS
COMPARATOR
CLOCK OUT
SERIAL/PARALLEL
SELECT
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT PARALLEL
LOAD
MASTER
RESET
+V
S
GND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
= 3.9 k
reference
AD9854–SPECIFICATIONS
(V = 3.3 V 5%, R frequency = externalwith REFCLKclock frequency = 30atMHz with
REFCLK Multiplier enabled at 10 for AD9854ASQ, external reference clock
20 MHz
Multiplier enabled 10 for
S
SET
AD9854AST unless otherwise noted.)
Parameter
REF CLOCK INPUT CHARACTERISTICS
1
Internal Clock Frequency Range
External REF Clock Frequency Range
REFCLK Multiplier Enabled
REFCLK Multiplier Disabled
Duty Cycle
Input Capacitance
Input Impedance
Differential Mode Common-Mode Voltage Range
Minimum Signal Amplitude
Common-Mode Range
V
IH
(Single-Ended Mode)
V
IL
(Single-Ended Mode)
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed
Resolution
I and Q Full-Scale Output Current
I and Q DAC DC Gain Imbalance
2
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
DAC DYNAMIC OUTPUT CHARACTERISTICS
I and Q DAC Quad. Phase Error
DAC Wideband SFDR
1 MHz to 20 MHz A
OUT
20 MHz to 40 MHz A
OUT
40 MHz to 60 MHz A
OUT
60 MHz to 80 MHz A
OUT
80 MHz to 100 MHz A
OUT
100 MHz to 120 MHz A
OUT
DAC Narrowband SFDR
10 MHz A
OUT
(± 1 MHz)
10 MHz A
OUT
(± 250 kHz)
10 MHz A
OUT
(± 50 kHz)
41 MHz A
OUT
(± 1 MHz)
41 MHz A
OUT
(± 250 kHz)
41 MHz A
OUT
(± 50 kHz)
119 MHz A
OUT
(± 1 MHz)
119 MHz A
OUT
(± 250 kHz)
119 MHz A
OUT
(± 50 kHz)
Residual Phase Noise
(A
OUT
= 5 MHz, Ext. CLK = 30 MHz,
REFCLK Multiplier Engaged at 10×)
1 kHz Offset
10 kHz Offset
100 kHz Offset
(A
OUT
= 5 MHz, Ext. CLK = 300 MHz,
REFCLK Multiplier Bypassed)
1 kHz Offset
10 kHz Offset
100 kHz Offset
Pipeline Delays
Phase Accumulator and DDS Core
Inverse Sinc Filter
Digital Multiplier
Temp
FULL
FULL
FULL
25°C
25°C
25°C
25°C
25°C
25°C
25°C
FULL
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Test
Level
VI
VI
VI
IV
IV
IV
IV
IV
IV
IV
I
IV
IV
I
I
I
I
I
IV
I
IV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Min
5
5
5
45
AD9854ASQ
Typ
Max
300
75
300
55
Min
5
5
5
45
AD9854AST
Typ
Max
200
50
200
55
Unit
MHz
MHz
MHz
%
pF
kΩ
mV p-p
V
V
V
MSPS
Bits
mA
dB
% FS
µA
LSB
LSB
kΩ
V
Degrees
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
50
3
100
50
3
100
800
1.6
2.3
1.75
1.9
1
300
800
1.6
2.3
1.75
1.9
1
200
5
–0.5
–6
12
10
+0.15
0.3
0.6
100
–0.5
0.2
58
56
52
48
48
48
83
83
91
82
84
89
71
77
83
20
+0.5
+2.25
2
1.25
1.66
+1.0
1
5
–0.5
–6
12
10
+0.15
0.3
0.6
100
–0.5
0.2
58
56
52
48
48
20
+0.5
+2.25
2
1.25
1.66
+1.0
1
83
83
91
82
84
89
25°C
25°C
25°C
V
V
V
140
138
142
140
138
142
dBc/Hz
dBc/Hz
dBc/Hz
25°C
25°C
25°C
25°C
25°C
25°C
V
V
V
IV
IV
IV
142
148
152
17
12
10
142
148
152
17
12
10
dBc/Hz
dBc/Hz
dBc/Hz
SysClk Cycles
SysClk Cycles
SysClk Cycles
–2–
REV. 0
AD9854
Parameter
MASTER RESET DURATION
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Hysteresis
COMPARATOR OUTPUT CHARACTERISTICS
Logic “1” Voltage, High Z Load
Logic “0” Voltage, High Z Load
Output Power, 50
Ω
Load, 120 MHz Toggle Rate
Propagation Delay
Output Duty Cycle Error
3
Rise/Fall Time, 5 pF Load
Toggle Rate, High Z Load
Toggle Rate, 50
Ω
Load
Output Cycle-to-Cycle Jitter
4
COMPARATOR NARROWBAND SFDR
4
10 MHz (± 1 MHz)
10 MHz (± 250 kHz)
10 MHz (± 50 kHz)
41 MHz (± 1 MHz)
41 MHz (± 250 kHz)
41 MHz (± 50 kHz)
119 MHz (± 1 MHz)
119 MHz (± 250 kHz)
119 MHz (± 50 kHz)
CLOCK GENERATOR OUTPUT JITTER
5
5 MHz A
OUT
40 MHz A
OUT
100 MHz A
OUT
PARALLEL I/O TIMING CHARACTERISTICS
T
ASU
(Address Setup Time to
WR
Signal Active)
T
ADHW
(Address Hold Time to
WR
Signal Inactive)
T
DSU
(Data Setup Time to
WR
Signal Inactive)
T
DHD
(Data Hold Time to
WR
Signal Inactive)
T
WRLOW
(WR Signal Minimum Low Time)
T
WRHIGH
(WR Signal Minimum High Time)
T
WR
(WR Signal Minimum Period)
T
ADV
(Address to Data Valid Time)
T
ADHR
(Address Hold Time to
RD
Signal Inactive)
T
RDLOV
(RD Low-to-Output Valid)
T
RDHOZ
(RD High-to-Data Three-State)
SERIAL I/O TIMING CHARACTERISTICS
T
PRE
(CS Setup Time)
T
SCLK
(Period of Serial Data Clock)
T
DSU
(Serial Data Setup Time)
T
SCLKPWH
(Serial Data Clock Pulsewidth High)
T
SCLKPWL
(Serial Data Clock Pulsewidth Low)
T
DHLD
(Serial Data Hold Time)
T
DV
(Data Valid Time)
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Temp
25°C
25°C
25°C
25°C
25°C
FULL
FULL
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
25°C
25°C
25°C
25°C
25°C
Test
Level
IV
V
IV
I
IV
VI
VI
I
IV
I
V
IV
IV
IV
V
V
V
V
V
V
V
V
V
V
V
V
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
I
I
IV
IV
V
8.2
0
2.1
0
2.2
7
10
15
5
3.1
0.16
9
–10
300
375
11
3
±
1
2
350
400
9
+10
–10
300
375
4.0
84
84
92
76
82
89
73
73
83
23
12
7
7.8
1.6
1.8
8.2
0
2.1
0
2.2
7
10
15
5
84
84
92
76
82
89
73
73
83
23
12
7
7.8
1.6
1.8
11
3
±
1
2
350
400
AD9854ASQ
Min
Typ
Max
10
3
500
±
1
10
AD9854AST
Min
Typ
Max
10
3
500
±
1
10
3.1
0.16
Unit
SysClk Cycles
pF
kΩ
µA
mV p-p
V
V
dBm
ns
%
ns
MHz
MHz
ps rms
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
ps rms
ps rms
ps rms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
µA
µA
pF
±
5
20
±
5
20
+10
4.0
15
15
10
15
15
10
30
100
30
40
40
0
30
2.7
0.4
±
5
±
5
3
30
100
30
40
40
0
30
2.7
0.4
±
12
±
12
3
REV. 0
–3–
AD9854–SPECIFICATIONS
Parameter
POWER SUPPLY
6
+V
S
Current
7
+V
S
Current
8
+V
S
Current
9
P
DISS7
P
DISS8
P
DISS9
P
DISS
Power-Down Mode
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Test
Level
I
I
I
I
I
I
I
Min
AD9854ASQ
Typ
Max
1050
710
600
3.475
2.345
1.975
1
1210
816
685
4.190
2.825
2.375
50
Min
AD9854AST
Typ
Max
755
515
435
2.490
1.700
1.435
1
865
585
495
3.000
2.025
1.715
50
Unit
mA
mA
mA
W
W
W
mW
NOTES
1
The reference clock inputs are configured to accept a 1 V p-p (minimum) dc offset sine wave centered at one-half the applied V
DD
or a 3 V TTL-level pulse input.
2
The I and Q gain imbalance is digitally adjustable to less than 0.01 dB.
3
Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.
4
Represents comparator’s inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device Wavecrest DTS – 2075.
5
Comparator input originates from analog output section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50
Ω.
6
Simultaneous operation at the maximum ambient temperature of 85
°C
and the maximum internal clock frequency of 200 MHz for the 80-lead LQFP, or 300 MHz
for the thermally-enhanced 80-lead LQFP may cause the maximum die junction temperature of 150
°C
to be exceeded. Refer to the section titled Power Dissipation
and Thermal Considerations for derating and thermal management information.
7
All functions engaged.
8
All functions except inverse sinc engaged.
9
All functions except inverse sinc and digital multipliers engaged.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
ABSOLUTE MAXIMUM RATINGS*
I
– 100% Production Tested.
III – Sample Tested Only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing
for industrial operating temperature range.
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V
S
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Maximum Clock Frequency . . . . . . . . . . . . . . . . . . 300 MHz
*Absolute
maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect device
reliability.
ORDERING GUIDE
Model
AD9854ASQ
AD9854AST
AD9854/PCB
Temperature Range
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
Package Description
Thermally-Enhanced 80-Lead LQFP
80-Lead LQFP
Evaluation Board
Package Option
SQ-80
ST-80
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9854 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD9854
PIN FUNCTION DESCRIPTIONS
Pin
No.
1–8
9, 10, 23,
24, 25, 73,
74, 79, 80
11, 12, 26,
27, 28, 72,
75, 76, 77,
78
13, 35, 57,
58, 63
14–19
(17)
Pin Name
D7–D0
DVDD
Function
Eight-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.
Connections for Digital Circuitry Ground Return. Same potential as AGND.
DGND
NC
A5–A0
A2/IO RESET
No Internal Connection.
Six-Bit Parallel Address Inputs for Program Registers. Used only in parallel programming mode. A0, A1,
and A2 have a second function when the serial programming mode is selected. See immediately below.
Allows a RESET of the serial communications bus that is unresponsive due to improper program-
ming protocol. Resetting the serial bus in this manner does not affect previous programming nor
does it invoke the “default” programming values seen in the Table V. Active HIGH.
Unidirectional Serial Data Output for Use in 3-Wire Serial Communication Mode.
Bidirectional Serial Data Input/Output for Use in 2-Wire Serial Communication Mode.
Bidirectional Frequency Update Signal. Direction is selected in control register. If selected as an input,
a rising edge will transfer the contents of the programming registers to the internal works of the IC for
processing. If I/O UD is selected as an output, an output pulse (low to high) of eight system clock cycle
duration indicates that an internal frequency update has occurred.
Write Parallel Data to Programming Registers. Shared function with SCLK. Serial clock signal
associated with the serial programming bus. Data is registered on the rising edge. This pin is shared with
WRB when the parallel mode is selected.
Read Parallel Data from Programming Registers. Shared function with CSB. Chip-select signal
associated with the serial programming bus. Active LOW. This pin is shared with RDB when
the parallel mode is selected.
Multifunction Pin According to the Mode of Operation Selected in the Programming Control Register.
If in the FSK mode logic low selects F1, logic high selects F2. If in the BPSK mode, logic low selects
Phase 1, logic high selects Phase 2. If in the Chirp mode, logic high engages the HOLD function
causing the frequency accumulator to halt at its current location. To resume or commence Chirp,
logic low is asserted.
Must First Be Selected in the Programming Control Register to Function. A logic high will cause the
I and Q DAC outputs to ramp-up from zero-scale to full-scale amplitude at a preprogrammed rate.
Logic low causes the full-scale output to ramp-down to zero-scale at the preprogrammed rate.
Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND
Connections for Analog Circuitry Ground Return. Same potential as DGND.
(18)
(19)
20
A1/SDO
A0/SDIO
I/O UD
21
WRB/SCLK
22
RDB/CSB
29
FSK/BPSK/
HOLD
30
SHAPED
KEYING
AVDD
31, 32, 37,
38, 44, 50,
54, 60, 65
33, 34, 39,
40, 41, 45,
46, 47, 53,
59, 62, 66,
67
36
42
43
48
49
51
52
AGND
VOUT
VINP
VINN
IOUT1
IOUT1B
IOUT2B
IOUT2
Internal High-Speed Comparator’s Noninverted Output Pin. Designed to drive 10 dBm to 50
Ω
load
as well as standard CMOS logic levels.
Voltage Input Positive. The internal high-speed comparator’s noninverting input.
Voltage Input Negative. The internal high-speed comparator’s inverting input.
Unipolar Current Output of the I or Cosine DAC.
Complementary Unipolar Current Output of the I or Cosine DAC.
Complementary Unipolar Current Output of the Q or Sine or DAC.
Unipolar Current Output of the Q or Sine DAC. This DAC can be programmed to accept
external 12-bit data in lieu of internal sine data. This allows the AD9854 to emulate the AD9852
control DAC function.
REV. 0
–5–
展开预览

猜您喜欢

推荐帖子

评论

加载更多
登录/注册

意见反馈

求资源

回顶部

上传资源

上传者
1615371962
查看他的其他资源


TI 文字链专区

汽车 模拟

推荐内容

开源项目推荐 更多

热门活动

热门器件

用户搜过

随便看看

热门下载

热门标签

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版 版权声明

EEWorld电子技术资料下载——分享有价值的资料

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编：100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved
×