CMOS 300 MSPS Quadrature
Complete DDS
AD9854
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit digital-to-analog converters (DACs)
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) A
OUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and
on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via input/output interface
Linear or nonlinear FM chirp functions with single-pin
frequency hold function
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interfaces
10 MHz serial 2- or 3-wire SPI compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile, quadrature LO frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciters
FUNCTIONAL BLOCK DIAGRAM
SYSTEM CLOCK
FREQUENCY
ACCUMULATOR
ACC 1
PHASE
ACCUMULATOR
ACC 2
48
48
17
17
PHASE-TO-
AMPLITUDE
CONVERTER
MUX
REFERENCE
CLOCK IN
REF
CLK
BUFFER
4× TO 20×
REF CLK
MULTIPLIER
DDS CORE
I
MUX
12
INV
SINC
FILTER
DIGITAL MULTIPLIERS
12
12-BIT
I
DAC
ANALOG
OUT
DAC R
SET
12-BIT
Q DAC OR
CONTROL
DAC
ANALOG
OUT
DIFF/SINGLE
SELECT
SYSTEM
CLOCK
Q
DEMUX
FSK/BPSK/HOLD
DATA IN
3
MUX
DELTA
FREQUENCY
RATE TIMER
2
48 SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
48
48
14
MUX
MUX
SYSTEM
CLOCK
14
12
12
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
12
12
COMPARATOR
CLOCK
OUT
ANALOG
IN
FREQUENCY
TUNING
WORD 1
I AND Q 12-BIT
FREQUENCY
FIRST 14-BIT
SECOND 14-BIT
12-BIT DC
TUNING
PHASE/OFFSET PHASE/OFFSET AM MODULATION CONTROL
WORD 2
WORD
WORD
PROGRAMMING REGISTERS
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
MODE SELECT
SYSTEM
CK
CLOCK
Q
D
INT
EXT
MUX
48
14
MUX
SYSTEM
CLOCK
MUX
12
INV
SINC
FILTER
12
OSK
BUS
I/O PORT BUFFERS
GND
+V
S
÷2
SYSTEM
CLOCK
AD9854
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
READ
WRITE
SERIAL/
PARALLEL
SELECT
Figure 1.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.
00636-001
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
AD9854
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
Explanation of Test Levels ........................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 12
Typical Applications ....................................................................... 16
Theory of Operation ...................................................................... 19
Modes of Operation ................................................................... 19
Using the AD9854 .......................................................................... 29
Internal and External Update Clock ........................................ 29
On/Off Output Shaped Keying (OSK) .................................... 29
I and Q DACs.............................................................................. 30
Control DAC ............................................................................... 30
Inverse Sinc Function ................................................................ 31
REFCLK Multiplier .................................................................... 31
Programming the AD9854............................................................ 32
MASTER RESET ........................................................................ 32
Parallel I/O Operation ............................................................... 34
Serial Port I/O Operation.......................................................... 34
General Operation of the Serial Interface ................................... 36
Instruction Byte .......................................................................... 37
Serial Interface Port Pin Descriptions ..................................... 37
Notes on Serial Port Operation ................................................ 37
MSB/LSB Transfers......................................................................... 38
Control Register Description.................................................... 38
Power Dissipation and Thermal Considerations ....................... 40
Thermal Impedance................................................................... 40
Junction Temperature Considerations .................................... 40
Evaluation of Operating Conditions........................................ 41
Thermally Enhanced Package Mounting Guidelines ................ 41
Evaluation Board ............................................................................ 42
Evaluation Board Instructions.................................................. 42
General Operating Instructions ............................................... 42
Using the Provided Software .................................................... 44
Support ........................................................................................ 44
Outline Dimensions ....................................................................... 52
Ordering Guide .......................................................................... 52
Rev. E | Page 2 of 52
AD9854
REVISION HISTORY
7/07—Rev. D to Rev. E
Changed AD9854ASQ to AD9854ASVZ ....................... Universal
Changed AD9854AST to AD9854ASTZ......................... Universal
Changes to General Description .....................................................4
Changes to Table 1 Endnotes...........................................................7
Changes to Absolute Maximum Ratings Section..........................8
Changes to Power Dissipation Section.........................................40
Changes to Thermally Enhanced Package Mounting
Guidelines Section......................................................................41
Changes to Figure 64 ......................................................................47
Changes to Outline Dimensions ...................................................52
Changes to Ordering Guide...........................................................52
11/06—Rev. C to Rev. D
Changes to General Description Section .......................................4
Changes to Endnotes in the Power Supply Parameter .................7
Changes to Absolute Maximum Ratings Section..........................8
Added Endnotes to Table 2 ..............................................................8
Changes to Figure 50 ......................................................................29
Changes to Power Dissipation Section.........................................39
Changes to Figure 68 ......................................................................45
Updated Outline Dimensions........................................................51
Changes to Ordering Guide...........................................................51
9/04—Rev. B to Rev. C
Updated Format.................................................................. Universal
Changes to Table 1 ............................................................................4
Changes to Footnote 2 ......................................................................7
Changes to Explanation of Test Levels Section .............................8
Changes to Theory of Operation Section ....................................17
Changes to Single Tone (Mode 000) Section...............................17
Changes to Ramped FSK (Mode 010) Section............................18
Changes to Basic FM Chirp Programming Steps Section .........23
Changes to Figure 50 ......................................................................27
Changes to Evaluation Board Operating Instructions Section.40
Changes to Filtered IOUT1 and the Filtered IOUT2 Section ...41
Changes to Using the Provided Software Section.......................42
Changes to Figure 68 ......................................................................45
Changes to Figure 69 ......................................................................46
Updated Outline Dimensions........................................................50
Changes to Ordering Guide...........................................................50
3/02—Rev. A to Rev. B
Updated Format ................................................................. Universal
Renumbered Figures and Tables ...................................... Universal
Changes to General Description Section.......................................1
Changes to Functional Block Diagram ..........................................1
Changes to Specifications Section ..................................................4
Changes to Absolute Maximum Ratings Section .........................7
Changes to Pin Function Descriptions ..........................................8
Changes to Figure 3 ........................................................................10
Deleted two Typical Performance Characteristics Graphs........11
Changes to Inverse SINC Function Section ................................28
Changes to Differential REFCLK Enable Section.......................28
Changes to Figure 52 ......................................................................30
Changes to Parallel I/O Operation Section .................................32
Changes to General Operation of the Serial Interface Section .33
Changes to Figure 57 ......................................................................34
Replaced Operating Instructions Section ....................................40
Changes to Figure 68 ......................................................................44
Changes to Figure 69 ......................................................................45
Changes to Customer Evaluation Board Table............................46
Rev. E | Page 3 of 52
AD9854
GENERAL DESCRIPTION
The AD9854 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with two internal
high speed, high performance quadrature DACs to form a digitally
programmable I and Q synthesizer function. When referenced
to an accurate clock source, the AD9854 generates highly stable,
frequency-phase, amplitude-programmable sine and cosine
outputs that can be used as an agile LO in communications, radar,
and many other applications. The innovative high speed DDS core
of the AD9854 provides 48-bit frequency resolution (1 μHz tuning
resolution with 300 MHz SYSCLK). Maintaining 17 bits ensures
excellent SFDR.
The circuit architecture of the AD9854 allows the generation of
simultaneous quadrature output signals at frequencies up to
150 MHz, which can be digitally tuned at a rate of up to
100 million new frequencies per second. The sine wave output
(externally filtered) can be converted to a square wave by the
internal comparator for agile clock generator applications.
The device provides two 14-bit phase registers and a single pin
for BPSK operation.
For higher-order PSK operation, the I/O interface can be used
for phase changes. The 12-bit I and Q DACs, coupled with the
innovative DDS architecture, provide excellent wideband and
narrow-band output SFDR. The Q DAC can also be configured
as a user-programmable control DAC if the quadrature function
is not desired. When configured with the comparator, the 12-bit
control DAC facilitates static duty cycle control in high speed
clock generator applications.
Two 12-bit digital multipliers permit programmable amplitude
modulation, on/off output shaped keying, and precise amplitude
control of the quadrature output. Chirp functionality is also
included to facilitate wide bandwidth frequency sweeping
applications. The programmable 4× to 20× REFCLK multiplier
circuit of the AD9854 internally generates the 300 MHz system
clock from an external lower frequency reference clock. This
saves the user the expense and difficulty of implementing a
300 MHz system clock source.
Direct 300 MHz clocking is also accommodated with either single-
ended or differential inputs. Single-pin conventional FSK and
the enhanced spectral qualities of ramped FSK are supported.
The AD9854 uses advanced 0.35 μm CMOS technology to
provide a high level of functionality on a single 3.3 V supply.
The AD9854 is pin-for-pin compatible with the AD9852 single-
tone synthesizer. It is specified to operate over the extended
industrial temperature range of −40°C to +85°C.
Rev. E | Page 4 of 52
AD9854
SPECIFICATIONS
V
S
= 3.3 V ± 5%, R
SET
= 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ,
external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854ASTZ, unless otherwise noted.
Table 1.
Parameter
REFERENCE CLOCK INPUT CHARACTERISTICS
1
Internal System Clock Frequency Range
REFCLK Multiplier Enabled
REFCLK Multiplier Disabled
External Reference Clock Frequency Range
REFCLK Multiplier Enabled
REFCLK Multiplier Disabled
Duty Cycle
Input Capacitance
Input Impedance
Differential Mode Common-Mode Voltage Range
Minimum Signal Amplitude
2
Common-Mode Range
V
IH
(Single-Ended Mode)
V
IL
(Single-Ended Mode)
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed
Resolution
I and Q Full-Scale Output Current
I and Q DAC DC Gain Imbalance
3
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
DAC DYNAMIC OUTPUT CHARACTERISTICS
I and Q DAC Quadrature Phase Error
DAC Wideband SFDR
1 MHz to 20 MHz A
OUT
20 MHz to 40 MHz A
OUT
40 MHz to 60 MHz A
OUT
60 MHz to 80 MHz A
OUT
80 MHz to 100 MHz A
OUT
100 MHz to 120 MHz A
OUT
DAC Narrow-Band SFDR
10 MHz A
OUT
(±1 MHz)
10 MHz A
OUT
(±250 kHz)
10 MHz A
OUT
(±50 kHz)
41 MHz A
OUT
(±1 MHz)
41 MHz A
OUT
(±250 kHz)
41 MHz A
OUT
(±50 kHz)
119 MHz A
OUT
(±1 MHz)
119 MHz A
OUT
(±250 kHz)
119 MHz A
OUT
(±50 kHz)
Temp
Test
Level
AD9854ASVZ
Min Typ
Max
AD9854ASTZ
Min Typ
Max
Unit
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
VI
VI
VI
VI
IV
IV
IV
IV
IV
IV
IV
I
IV
IV
I
I
I
I
I
IV
I
IV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
20
DC
5
DC
45
300
300
75
300
55
20
DC
5
DC
45
200
200
50
200
55
MHz
MHz
MHz
MHz
%
pF
kΩ
mV p-p
V
V
V
MSPS
Bits
mA
dB
% FS
μA
LSB
LSB
kΩ
V
Degrees
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
50
3
100
50
3
100
400
1.6
2.3
1.75
1.9
1
300
400
1.6
2.3
1.75
1.9
1
200
5
−0.5
−6
12
10
+0.15
0.3
0.6
100
−0.5
0.2
58
56
52
48
48
48
83
83
91
82
84
89
71
77
83
20
+0.5
+2.25
2
1.25
1.66
+1.0
1
5
−0.5
−6
12
10
+0.15
0.3
0.6
100
−0.5
0.2
58
56
52
48
48
48
83
83
91
82
84
89
71
77
83
20
+0.5
+2.25
2
1.25
1.66
+1.0
1
Rev. E | Page 5 of 52
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