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nRF51822数据手册

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这是最新版的51822数据手册

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nRF51822 Multiprotocol Bluetooth low energy24 GHz RF System on Chip Product Specification v31 Key Features Applications Computer peripherals and IO devices Mouse Keyboard Multitouch trackpad Interactive entertainment devices Remote control Gaming controller Beacons Personal Area Networks Healthfitness sensor and monitor devices Medical devices Keyfobs wrist watches Remote control toys 24 GHz transceiver 93 dBm sensitivity in Bluetooth low energy mode 250 kbps 1 Mbps 2 Mbps supp......

nRF51822
Multiprotocol
Bluetooth®
low energy/2.4 GHz RF System on Chip
Product Specification v3.1
Key Features
• 2.4 GHz transceiver
• -93 dBm sensitivity in
Bluetooth®
low energy mode
• 250 kbps, 1 Mbps, 2 Mbps supported data rates
• TX Power -20 to +4 dBm in 4 dB steps
• TX Power -30 dBm Whisper mode
• 13 mA peak RX, 10.5 mA peak TX (0 dBm)
• 9.7 mA peak RX, 8 mA peak TX (0 dBm) with DC/DC
• RSSI (1 dB resolution)
• ARM® Cortex™-M0 32 bit processor
• 275 μA/MHz running from flash memory
• 150 μA/MHz running from RAM
• Serial Wire Debug (SWD)
• S100 series SoftDevice ready
• Memory
• 256 kB or 128 kB embedded flash program memory
• 16 kB or 32 kB RAM
• On-air compatibility with nRF24L series
• Flexible Power Management
• Supply voltage range 1.8 V to 3.6 V
• 4.2 μs wake-up using 16 MHz RCOSC
• 0.6 μA at 3 V OFF mode
• 1.2 μA at 3 V in OFF mode + 1 region RAM retention
• 2.6 μA at 3 V ON mode, all blocks IDLE
• 8/9/10 bit ADC - 8 configurable channels
• 31 General Purpose I/O Pins
• One 32 bit and two 16 bit timers with counter mode
• SPI Master/Slave
• Low power comparator
• Temperature sensor
• Two-wire Master (I2C compatible)
• UART (CTS/RTS)
• CPU independent Programmable Peripheral Interconnect (PPI)
• Quadrature Decoder (QDEC)
• AES HW encryption
• Real Timer Counter (RTC)
• Package variants
• QFN48 package, 6 x 6 mm
• WLCSP package, 3.50 x 3.83 mm
• WLCSP package, 3.83 x 3.83 mm
• WLCSP package, 3.50 x 3.33 mm
Applications
• Computer peripherals and I/O devices
• Mouse
• Keyboard
• Multi-touch trackpad
• Interactive entertainment devices
• Remote control
• Gaming controller
• Beacons
• Personal Area Networks
• Health/fitness sensor and monitor
devices
• Medical devices
• Key-fobs + wrist watches
• Remote control toys
Copyright © 2014 Nordic Semiconductor ASA. All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
nRF51822 Product Specification v3.1
Liability disclaimer
Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to
improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out
of the application or use of any product or circuits described herein.
Life support applications
Nordic Semiconductor’s products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Nordic
Semiconductor ASA customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such
improper use or sale.
Contact details
For your nearest distributor, please visit
www.nordicsemi.com.
Information regarding product updates, downloads, and technical support can be accessed through your
My Page account on our home page.
Main office:
Otto Nielsens veg 12
7052 Trondheim
Norway
Phone: +47 72 89 89 00
Fax: +47 72 89 89 89
Mailing address:
Nordic Semiconductor
P.O. Box 2336
7004 Trondheim
Norway
RoHS and REACH statement
Nordic Semiconductor's products meet the requirements of Directive 2002/95/EC of the European
Parliament and of the Council on the Restriction of Hazardous Substances (RoHS) and the requirements of
the REACH regulation (EC 1907/2006) on Registration, Evaluation, Authorization and Restriction of
Chemicals. The SVHC (Substances of Very High Concern) candidate list is continually being updated.
Complete hazardous substance reports, material composition reports and latest version of Nordic's REACH
statement can be found on our website
www.nordicsemi.com.
Page 2
nRF51822 Product Specification v3.1
Datasheet Status
Status
Objective Product Specification (OPS)
Preliminary Product Specification (PPS)
Description
This product specification contains target specifications for product
development.
This product specification contains preliminary data; supplementary data
may be published from Nordic Semiconductor ASA later.
This product specification contains final product specifications. Nordic
Semiconductor ASA reserves the right to make changes at any time
without notice in order to improve design and supply the best possible
product.
Product Specification (PS)
Revision History
Date
October 2014
Version
3.1
Description
Added documentation for the following versions of the chip:
• nRF51822-QFAC AA0
• nRF51822-QFAC Ax0
• nRF51822-CDAB AA0
• nRF51822-CDAB Ax0
• nRF51822-CFAC AA0
• nRF51822-CFAC Ax0
(The x in the build codes can be any number between 0 and 9.)
Added content:
Section 2.2.2 “CDAB WLCSP ball assignment and functions”
on page 13
Section 9.2 “CDAB WLCSP package”
on page 67
Section 9.4 “CFAC WLCSP package”
on page 69
Updated content:
• Feature list on the front page.
Section 2.2.3 “CEAA and CFAC WLCSP ball assignment and functions”
on page 16
Section 3.2.1 “Code organization”
on page 21
Section 3.2.2 “RAM organization”
on page 21
Section 3.3 “Memory Protection Unit (MPU)”
on page 22
Section 8.2 “Power management”
on page 44
Section 8.3 “Block resource requirements”
on page 48
Section 8.12 “Analog to Digital Converter (ADC) specifications”
on page 60
Section 10.6 “Code ranges and values”
on page 73
Section 10.7 “Product options”
on page 75
Page 3
nRF51822 Product Specification v3.1
Date
August 2014
Version
3.0
Description
Update to reflect the changes in build code:
• nRF51822-QFAA Hx0
• nRF51822-CEAA Ex0
• nRF51822-QFAB Cx0
(The x in the build codes can be any number between 0 and 9.)
If you are working with a previous revision of the chip, read version 2.x of the document.
Added content:
Section 8.5.3 “Radio current consumption with DC/DC enabled”
on page 50
Section 11.1.1 “PCB layout example”
on page 77
Updated content:
• Feature list on the front page.
Section 2.1 “Block diagram”
on page 10
Section 3.2.1 “Code organization”
on page 21
Section 3.2.2 “RAM organization”
on page 21
Section 3.3 “Memory Protection Unit (MPU)”
on page 22
Section 3.4 “Power management (POWER)”
on page 23
Section 3.6 “Clock management (CLOCK)”
on page 27
Section 3.8 “Debugger support”
on page 30
Section 4.2 “Timer/counters (TIMER)”
on page 32
Chapter 5 “Instance table”
on page 36
Chapter 7 “Operating conditions”
on page 38
Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)”
on page 40
Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)”
on page 41
Section 8.1.4 “16 MHz RC oscillator (16M RCOSC)”
on page 42
Section 8.1.6 “32.768 kHz RC oscillator (32k RCOSC)”
on page 43
Section 8.1.7 “32.768 kHz Synthesized oscillator (32k SYNT)”
on page 43
Section 8.2 “Power management”
on page 44
Section 8.3 “Block resource requirements”
on page 48
Section 8.4 “CPU”
on page 48
Section 8.5.6 “Radio timing parameters”
on page 54
Section 8.5.7 “Antenna matching network requirements”
on page 54
Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications”
on page 55
Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications”
on page 56
Section 8.12 “Analog to Digital Converter (ADC) specifications”
on page 60
Section 8.13 “Timer (TIMER) specifications”
on page 61
Section 8.15 “Temperature sensor (TEMP)”
on page 61
Section 8.22 “Non-Volatile Memory Controller (NVMC) specifications”
on page 64
Section 8.24 “Low Power Comparator (LPCOMP) specifications”
on page 65
Section 9.2 “CDAB WLCSP package”
on page 67
Section 10.7.2 “Development tools”
on page 75
Chapter 11 “Reference circuitry”
on page 76
Page 4
nRF51822 Product Specification v3.1
Date
October 2013
Version
2.0
Description
This version of the document will target the nRF51822 QFAA G0 revision of the chip. If you
are working with a previous revision of the chip, read version 1.3 or earlier of the
document.
Updated
the following sections:
Key Feature list on the front page,
Chapter 1 “Introduction”
on page 9,
Section 2.1 “Block diagram”
on page 10,
Section 2.2 “Pin assignments and functions”
on page 11,
Section 3.2 “Memory”
on page 20,
Section 3.5 “Programmable Peripheral Interconnect (PPI)”
on page 26,
Section 3.7 “GPIO”
on page 30,
Section 4.1 “2.4 GHz radio (RADIO)”
on page 31,
Section 4.2 “Timer/counters (TIMER)”
on page 32,
Section 4.3 “Real Time Counter (RTC)”
on page 32,
Section 4.10 “Serial Peripheral Interface (SPI/SPIS)”
on page 34,
Section 4.12 “Universal Asynchronous Receiver/Transmitter (UART)”
on page 35,
Section 4.14 “Analog to Digital Converter (ADC)”
on page 35,
Section 4.15 “GPIO Task Event blocks (GPIOTE)”
on page 35,
Chapter 5 “Instance table”
on page 36,
Chapter 6 “Absolute maximum ratings”
on page 37,
Chapter 8 “Electrical specifications”
on page 39,
Section 8.1 “Clock sources”
on page 39,
Section 8.1.2 “16 MHz crystal oscillator (16M XOSC)”
on page 40,
Section 8.1.3 “32 MHz crystal oscillator (32M XOSC)”
on page 41,
Section 8.2 “Power management”
on page 44,
Section 8.3 “Block resource requirements”
on page 48,
Section 8.7 “Universal Asynchronous Receiver/Transmitter (UART) specifications”
on
page 55,
Section 8.9 “Serial Peripheral Interface (SPI) Master specifications”
on page 57,
Section 8.11 “GPIO Tasks and Events (GPIOTE) specifications”
on page 59,
Section 8.13 “Timer (TIMER) specifications”
on page 61,
Section 8.16 “Random Number Generator (RNG) specifications”
on page 62,
Section 8.17 “AES Electronic Codebook Mode Encryption (ECB) specifications”
on page 62,
Section 8.18 “AES CCM Mode Encryption (CCM) specifications”
on page 62,
Section 8.19 “Accelerated Address Resolver (AAR) specifications”
on page 62,
Section 8.21 “Quadrature Decoder (QDEC) specifications”
on page 63,
Section 11.1 “PCB guidelines”
on page 76,
Section 11.3 “QFAA QFN48 package”
on page 79, and
Section 11.7 “CEAA WLCSP package”
on page 103.
Added
the following sections:
Section 3.3 “Memory Protection Unit (MPU)”
on page 22,
Section 4.5 “AES CCM Mode Encryption (CCM)”
on page 33,
Section 4.6 “Accelerated Address Resolver (AAR)”
on page 33,
Section 4.16 “Low Power Comparator (LPCOMP)”
on page 35,
Section 8.5.7 “Antenna matching network requirements”
on page 54,
Section 8.8 “Serial Peripheral Interface Slave (SPIS) specifications”
on page 56,
Section 8.18 “AES CCM Mode Encryption (CCM) specifications”
on page 62,
Section 8.19 “Accelerated Address Resolver (AAR) specifications”
on page 62, and
Section 8.24 “Low Power Comparator (LPCOMP) specifications”
on page 65.
May 2013
1.3
Updated schematics and BOMs in section 11.3 on page 61.
Page 5
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