nRF51 Series Reference Manual
Version 1.1
The nRF51 series offers a range of ultra-low power System on Chip solutions for your
2.4 GHz wireless products. With the nRF51 series you have a diverse selection of
devices including those with embedded
Bluetooth®
low energy and/or ANT
protocol stacks as well as open devices enabling you to develop your own
proprietary wireless stack and ecosystem.
TM
The nRF51 series combines Nordic Semiconductor’s leading 2.4 GHz transceiver
technology with a powerful but low power ARM® Cortex -M0 core, a range of
peripherals and memory options. The pin and code compatible devices of the
nRF51 series offer you the most flexible platform for all your 2.4 GHz wireless
applications.
TM
All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
2013-03-08
nRF51 Series Reference Manual v1.1
Liability disclaimer
Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to
improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out
of the application or use of any product or circuits described herein.
Life support applications
Nordic Semiconductor’s products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Nordic
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Revision History
Date
March 2013
Version
1.1
•
Description
Updated DC/DC converter setup
description in
section 11.1.1.1 on
page 36.
Updated values in
section 16.1.8
on page 73.
First release
•
January 2013
1.0
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nRF51 Series Reference Manual v1.1
1
About this document
This reference manual is a functional description of all the modules and peripherals supported by the nRF51
series and subsequently, is a common document for all nRF51 System on Chip (SoC) devices.
Note:
nRF51 SoC devices may not support all the modules and peripherals described in this
document and some of their implemented modules may have a reduced feature set. Please
refer to the individual nRF51 device product specification for details on the supported feature
set, electrical and mechanical specifications, and application specific information.
1.1
Writing conventions
This Reference Manual follows a set of typographic rules to ensure that the document is consistent and easy
to read. The following writing conventions are used:
•
•
•
•
•
Command and event names, and bit state conditions are written in
Lucida Console
.
Pin names and pin signal conditions are written in
Consolas
.
File names and User Interface components are written in
bold.
Internal cross references are italicized and written in
semi-bold.
Placeholders for parameters are written in
italic regular font.
For example, a syntax
description of SetChannelPeriod will be written as: SetChannelPeriod(ChannelNumber,
MessagingPeriod).
• Fixed parameters are written in regular text font. For example, a syntax description of
SetChannelPeriod will be written as: SetChannelPeriod (0, Period).
1.1.1
Peripheral naming and abbreviations
Every peripheral has a unique name or an abbreviation constructed by a single word, e.g. TIMER. This name
is indicated in parentheses in the peripheral chapter heading. This name will be used in CMSIS to identify
the peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using the
peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normally
only used if a peripheral can be instantiated more than once. The peripheral instance name is also used in
the CMSIS to identify the peripheral instance.
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nRF51 Series Reference Manual v1.1
1.1.2
Register tables
Individual registers are described using register tables. These tables are built up of two sections. The first
three rows, which are shaded blue, describe the position and size of the different fields in the register. The
following rows, beginning with the row shaded green, describes the fields in more detail.
Bit number
ID (Field ID)
Reset value
ID RW
A RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
1 -
1 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- - A A A A A A A A
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0 0 0 0 0 0 0
Field Value ID Value
Description
Register with a single field without enumerated values
Table 1
Example of a register table with a single field
1.1.2.1
Fields and values
The
ID (Field ID)
row specifies which bits that belong to the different fields in the register.
The
ID (Field ID)
may also specify constants. ‘1’ in this row means that the associated bit is read as ‘1’ and
must be written as ‘1’. Similarly, ‘0’ means that the associated bit is read as ‘0’ and must be written as ‘0’. A “-“
means that the field is reserved and that it is read as undefined and must be written as ‘0’ to secure forward
compatibility. If a register is divided into more than one field, a unique field name is specified for each field
in the
Field
column.
If a field has enumerated values, then every value will be identified with a unique value ID in the
Value ID
column. Single-bit bit-fields may however omit the “Value ID” when values can be substituted with a
Boolean type enumerator range, for example, True, False; Disable, Enable, and On, Off, and so on.
The
Value
column can be populated in the following ways:
• Individual enumerated values, for example, 1, 3, 9.
• Range values, e.g. [0..4], that is, all values from and including 0 and 4.
• Implicit values. If no values are indicated in the
Value
column, all bit combinations are
supported, or alternatively the field’s translation and limitations are described in the text
instead.
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nRF51 Series Reference Manual v1.1
If two or more fields are closely related, the value ID, value, and description may be omitted for all but the
first field. Subsequent fields will indicate inheritance with “..”.
Bit number
ID (Field ID)
Reset value
ID RW
A RW
B RW
Field
RANGE
ENUM
ENUMA
ENUMB
ENUMC
C RW
IMP0
0
1
D RW
E RW
F RW
IMP1
IMP2
IMP3
..
..
..
0
4
15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
1
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
F
0
E D C
0
0
0
-
0
-
- - B B B B A A A A
0 0 0 0 0 0 0 0 0 0 0
Value ID Value
[0..15]
Description
Range description uses this syntax
Fields with enumerated values are described like this
First enumerated value
Second enumerated value
Third enumerated value
Register for IMP number 0 with implicit enumerated values, acting as parent for
subsequent IMP registers.
Disable
Enable
..
..
..
Table 2
Example of a register table with multiple fields
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