Slides for
『超高速I/O
ESD保護電路標準工½小組』
Guideline Suggestion
for High-Speed I/O ESD Protection
柯明道
教授
(Prof. Ming-Dou Ker)
交通大學電子研究所 奈米電子及晶片系統實驗室
Nanoelectronics & Gigascale Systems Laboratory
Institute of Electronics
National Chiao-Tung University, Hsinchu, Taiwan
mdker@ieee.org
1
Nov. 2005
Ker’05
I/O Cells with ESD Protection Design
2
Ker’05
General ESD Specifications for IC Products
Component-Level ESD:
HBM
Okay
Safe
Super
+/- 2kV
+/- 4kV
+/- 10kV
MM
+/- 200V
+/- 400V
+/- 1kV
CDM
+/- 1kV
+/- 1.5kV
+/- 2kV
Basic
Request
An IC during ESD test with all pin combinations has to
pass above ESD specifications (both positive and negative
ESD voltages).
ESD failure criterion including pin leakage current and
all function testing.
3
Ker’05
Conventional Input ESD Protection Circuit
for Digital Pin
VDD
Mp
I
ESD
Input
Pad
+V
I
ESD
Primary
ESD
Protection
R
I
ESD
V
ESD
0V
Mn
NMOS
I
ESD
Secondary
ESD
Protection
VSS
I
I
t2
Snapback
(V
t2
,
I
t2
)
V
t1
< V
(gate-oxide breakdown)
V
on
<
(I
t2
X
R
+ V
t2
)
0
V
sb
Gate-Oxide
Breakdown
V
t1
V
Ker’05
4
Conventional Input ESD Protection Circuit
for Analog Pin
VDDA
Load
Circuits
I
ESD
Input
Pad
ggNMOS
X
I
ESD
Analog
Circuits
+V
V
ESD
0V
ESD
Clamp
C
j
VSSA
Analog Input Stage
The large and voltage-dependent nonlinear input capacitance from the ESD clamp device
causes a degradation on the precision of an ADC from 14-bit to become only 10-bit.
( I. E. Opris, “Bootstrapped pad protection structure,”
IEEE Journal of Solid-State Circuits,
pp. 300-301,
Feb. 1998.)
5
Ker’05
Cross-Sectional View of gate-grounded
NMOS (ggNMOS) for ESD Protection
Input
Pad
Silicide
Diffusion
VSS
S
G
VSS
G
S
Silicide
Blocking
Silicide
Blocking
P+
N+
N+
LDD
Drain
LDD
N+
C
j
C
j
P-well
P-substrate
6
Ker’05
gate-grounded NMOS (ggNMOS)
with ESD Implantation
VSS
Silicide
Diffusion
Input
Pad
Silicide
Blocking
Silicide
Blocking
VSS
G
S
S
G
P+
N+
N+
LDD
LDD
N+
C
jgate
C
jgate
Cj
P-well
P-substrate
7
ESD Implantation
Ker’05
Input Capacitance Specification
in Giga-Hz RF ICs
Bond pad
Small bond pad size
Maximum
for 2-GHz RF input
200 fF
Pad
Pad
ESD devices
Small area and High
ESD robustness : SCR (?)
Ref.: C Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and P. Mortini, “Investigation on different ESD
protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18um CMOS process,” in
Pro. of
EOS/ESD Sym.,
2000, pp.251-259.
8
Ker’05
Consideration of ESD Protection Design
for RF (Giga-Hz) Circuits
Input impedance matching.
ESD devices is a source of thermal noise.
ESD devices is a media to couple substrate
noise.
RF modeling on ESD devices.
9
Ker’05
Diode Structure Using as ESD Protection Device
Cathode
W = 50, 100, 150 (µm)
L= 1.5(µm)
Anode
10
Ker’05
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