作者：Sedigheh Hashemi，Behzad Razavi
摘要：A two-stage pipelined ADC employs a double-sampling residue amplifier, two interleaved precharged DACs, and a new calibration scheme to correct for residue gain error, offset, and nonlinearity. The coarse and fine stages are implemented as flash ADCs incorporating several techniques to reduce their power, complexity, and kickback noise. Realized in 65 nm CMOS technology and sampling at 1 GHz, the prototype achieves an SNDR of 48 dB at the Nyquist rate and exhibits an FOM of 25 fJ/conversion- step while drawing 7.1 mW from a 1 V supply.
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