Impedance Matching Techniques for VLSI PackagingProblem Statement•Reflections from interconnect will limit VLSI system performance•This is caused by :1) Parasitics of the Package Interconnect2) Faster Risetimes in Off-chip Driver CircuitryAgenda1) Package Interconnect Parasitics2) Proposed Solution3) Experimental ResultsWhy is packaging limiting performance?•Today’s Package Interconnect Looks Inductive -Long interconnect paths-Large return loops
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