®
Designing Stable Compensation Networks for
Single Phase Voltage Mode Buck Regulators
Technical Brief
December 2003
TB417.1
Author: Doug Mattingly
Assumptions
This Technical Brief makes the following assumptions:
1. The power supply designer has already designed the
power stage of the single phase buck converter. The last
step to the design is the compensation network.
2. The designer has at least a basic understanding of
control systems theory.
3. The designer has a basic understanding of Bode plots.
Output Filter
The output filter consists of the output inductor and all of the
output capacitance. It is important to include the DC
resistance (DCR) of the output inductor and the total
Equivalent Series Resistance (ESR) of the output capacitor
bank. The input to the output filter is the PHASE node and
the output is the regulator output. Figure 3 shows the
equivalent circuit of the output filter and its transfer function.
L
O
PHASE
C
O
ESR
DCR
V
OUT
Introduction
Synchronous and non-synchronous buck regulators have
three basic blocks that contribute to the closed loop system.
These blocks consist of the modulator, the output filter, and
the compensation network which closes the loop and
stabilizes the system.
ERROR
AMPLIFIER
+
REFERENCE
_
MODULATOR
OUTPUT
FILTER
OUTPUT
GAIN
FILTER
1 + s
⋅
ES R
⋅
C OUT
= ---------------------------------------------------------------------------------------------------------------------------------------
-
2
1 + s
⋅ (
ESR + DCR
) ⋅
C
+s
⋅
L
⋅
C
OUT
OUT
OUT
FIGURE 3. THE OUTPUT FILTER
COMPENSATION
NETWORK
FIGURE 1. BASIC BLOCKS OF THE BUCK REGULATOR
Modulator
The modulator is shown in Figure 2. The input to the
modulator is the output of the error amplifier, which is used
to compare the output to the reference.
V
IN
OSC
∆V
OSC
OUTPUT OF
ERROR AMPLIFIER
DRIVER
PWM
COMPARATOR
-
+
PHASE
DRIVER
The transfer function for the output filter shows the well
known double pole of an LC filter. It is important to note that
the ESR of the capacitor bank and the DCR of the inductor
both influence the damping of this resonant circuit. It is also
important to notice the single zero that is a function of the
output capacitance and its ESR.
Open Loop System
Figure 4 illustrates the open loop system and presents the
transfer function.
L
O
-
+
DCR
V
OUT
E/A
OUTPUT
C
O
ESR
FIGURE 2. THE MODULATOR
The output of the modulator is the PHASE node. The gain of
the modulator is simply the input voltage to the regulator,
V
IN
, divided by the peak-to-peak voltage of the oscillator,
∆V
OSC
, or:
V IN
-
GAIN MODULATOR
= ---------------------
∆V
OSC
V
1
+
s
⋅
ESR
⋅
C
IN
OUT
GAINOPENLOOP
=
---------------------
⋅
---------------------------------------------------------------------------------------------------------------------------------------
-
∆V
2
OSC
1
+
s
⋅ (
ESR + DCR
) ⋅
C
+
s
⋅
L
⋅
C
OUT
OUT
OUT
FIGURE 4. THE OPEN LOOP SYSTEM
The peak to peak voltage of the oscillator can be obtained
from the data sheet for the controller IC.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Technical Brief 417
Figure 5 shows the asymptotic Bode plot of the open loop
system gain.
V
IN
20
⋅
log
---------------
-
∆V
pp
GAIN (dB)
Figure 7 shows the closed loop system with a Type II
compensation network and presents the closed loop transfer
function.
The following guidelines will help calculate the poles and
zeroes, and from those the component values, for a Type II
network.
1. Choose a value for R
1
, usually between 2k and 5kΩ.
0
F
ESR
F
LC
-40dB/DEC
-20dB/DEC
FREQUENCY (Hz)
FIGURE 5. OPEN LOOP SYSTEM GAIN
2. Pick a gain (R
2
/R
1
) that will shift the Open Loop Gain up
to give the desired bandwidth. This will allow the 0dB
crossover to occur in the frequency range where the
Type II network has a flat gain. The following equation will
calculate an R
2
that will accomplish this given the system
parameters and a chosen R
1
.
F ESR
2 DBW
∆V
OSC
-
-
-
R 2
=
----------------
⋅
----------------
⋅
---------------------
⋅
R 1
V IN
F LC
F ESR
Figure 5 represents a generic open loop system. Specific
systems will have different double pole and ESR zero
frequencies. For systems with very low DCR and ESR
parameters, the phase will experience a very sharp slope
downward at the double pole while the gain will have a
rather high peak at the double pole. Systems that have such
resonant output filters will be more difficult to compensate
since the phase will need an extra boost to provide the
necessary phase margin for stability. Systems such as this
will typically need a Type III compensation, which will be
discussed later in this brief.
3. Calculate C
2
by placing the zero a decade below the
output filter double pole frequency:
10
-
C 2
= -----------------------------------
2π
⋅
R 2
⋅
F LC
4. Calculate C
1
by placing the second pole at half the
switching frequency:
C2
C 1
= ----------------------------------------------------
-
π ⋅
R 2
⋅
C 2
⋅
F sw
–
1
Closing The Loop - The Compensation
Network
Closing the control loop allows the regulator to adjust to load
perturbations or changes in the input voltage which may
adversely affect the output. Proper compensation of the
system will allow for a predictable bandwidth with
unconditional stability. In most cases, a Type II or Type III
compensation network will properly compensate the system.
The ideal Bode plot for the compensated system would be a
gain that rolls off at a slope of -20dB/decade, crossing 0db at
the desired bandwidth and a phase margin greater than 45
o
for all frequencies below the 0dB crossing. For synchronous
and non-synchronous buck converters, the bandwidth
should be between 20 to 30% of the switching frequency.
Figure 8 shows the asymptotic Bode gain plot and the actual
gain and phase equations for the Type II compensated
system. It is recommended that the actual gain and phase
plots be generated through the use of commercially
available analytical software. Some examples of software
that can be used are Mathcad, Maple, and Excel. The
asymptotic plot of the gain and phase does not portray all
the necessary information that is needed to determine
stability and bandwidth.
The compensation gain must be compared to the open loop
gain of the error amplifier. The compensation gain should
not exceed the error amplifier open loop gain because this is
the limiting factor of the compensation. Once the gain and
phase plots are generated and analyzed, the system may
need to be changed somewhat in order adjust the bandwidth
or phase margin. Adjust the location of the pole and/or zero
to modify the profile of the plots.
If the phase margin proves too difficult to correct, then a
Type III system may be needed.
Type II Compensation
Figure 6 shows a generic Type II compensation, its transfer
function and asymptotic Bode plot. The Type II network
helps to shape the profile of the gain with respect to
frequency and also gives a 90
o
boost to the phase. This
boost is necessary to counteract the effects of the resonant
output filter at the double pole.
If the output voltage of the regulator is not the reference
voltage then a voltage programming resistor will be
connected between the inverting input to the error amplifier
and ground. This resistor is used to offset the output voltage
to a level higher than the reference. This resistor, if present,
has no effect on the compensation and can be ignored.
2
Technical Brief 417
.
C
1
R
2
C
2
1
s
+ -------------------
-
R
⋅
C
2
2
1
-
-
= -------------------
⋅
-------------------------------------------------------
GAIN
TYPEII
R
⋅
C
C
+
C
1
1
1
2
s
⋅
s
+ -------------------------------
-
R
⋅
C
⋅
C
2
1
2
-
R
1
V
OUT
REFERENCE
+
V
COMP
GAIN (dB)
-20dB/DEC
1
-------------------------------
2π
⋅
R 2
⋅
C 2
1
-------------------------------
2π
⋅
R 1
⋅
C 1
1
---------------------------------------------------
C1
⋅
C2
2π
⋅
R
⋅
---------------------
-
2
C
+
C
1
2
R
2
20
⋅
log
-------
R
1
0
-20dB/DEC
FREQUENCY (Hz)
0
FREQUENCY (Hz)
-30
PHASE
90
o
PHASE
“BOOST”
-60
-90
FIGURE 6. GENERIC TYPE II NETWORK
3
Technical Brief 417
.
V
IN
OSC
∆V
OSC
PWM
COMPARATOR
-
+
DRIVER
L
O
PHASE
C
O
ESR
DCR
V
OUT
C
1
C
2
R
2
DRIVER
R
1
V
COMP
-
+
REFERENCE
1
s
+ -------------------
-
V IN
1
+
s
⋅
ESR
⋅
C OUT
R
⋅
C
1
2
2
-
-
=
-------------------
⋅
-------------------------------------------------------
⋅
---------------------
⋅
----------------------------------------------------------------------------------------------------------------------------------------
GAIN
-
SYSTEM
2
R
⋅
C
C 1
+
C 2
∆V
OSC
1
1
1
+
s
⋅ (
ESR + DCR
) ⋅
C
+
s
⋅
L
⋅
C
OUT
OUT
OUT
s
⋅
s
+ -------------------------------
-
R
⋅
C
⋅
C
2
1
2
FIGURE 7. CLOSED LOOP SYSTEM WITH TYPE II NETWORK
ERROR AMP
DC GAIN
OPEN LOOP
ERROR AMP GAIN
GAIN (dB)
GAIN BANDWIDTH
PRODUCT
0.1F
LC
0
MODULATOR
& FILTER GAIN
-20dB/DEC
CONVERTER
GAIN
F
LC
F
ESR
BANDWIDTH
COMPENSATION
GAIN
0.5 F
SW
FREQUENCY
GAIN dB
(
f
)
=
GAIN MODULATOR
+
GAIN FILTER
+
GAIN TYPEII
PHASE
(
f
)
=
PHASE MODULATOR
+
PHASE FILTER
+
PHASE TYPEII
V IN
Where:
GAIN
-
=
20
⋅
log
---------------------
MODULATOR
∆V
OSC
GAIN FILTER
=
10
⋅
log 1
+
(
2πf
⋅
ESR
⋅
C OUT
)
2
2
2
2
+
(
2πf
⋅ (
ESR
+
DCR
) ⋅
C
–
10
⋅
log
1
–
(
2πf
) ⋅
L
⋅
OUT
)
OUT C OUT
2πf
⋅
ESR
+
DCR
⋅
C
OUT
-
PHASE FILTER
=
atan
[
2πf
⋅
ESR
⋅
C OUT
]
+
atan
---------------------------------------------------------------------
2
2πf
⋅
L OUT
⋅
C OUT
–
1
C1
⋅
C2
2
–
20
⋅
log
[
2πf
⋅
R
⋅ (
C
+
C
) ]
–
10
⋅
log 1
+
2πf
⋅
R
⋅
---------------------
-
1
1
2
2
C
+
C
1
2
C1
⋅
C2
o
-
PHASE TYPEII
=
–
90
+
atan
[
2πf
⋅
R 2
⋅
C 2
]
–
atan 2πf
⋅
R2
⋅
---------------------
C 1
+
C 2
GAIN
=
10
⋅
log 1
+
(
2πf
⋅
R
⋅
C
)
TYPEII
2
2
2
FIGURE 8. TYPE II COMPENSATED NETWORK
4
Technical Brief 417
Type III Compensation
Figure 9 shows a generic Type III compensation, its transfer
function and asymptotic Bode plot. The Type III network
shapes the profile of the gain with respect to frequency in a
similar fashion to the Type II network. The Type III network,
however, utilizes two zeroes to give a phase boost of 180
o
.
This boost is necessary to counteract the effects of an under
damped resonance of the output filter at the double pole.
Figure 10 shows the closed loop system with a Type III
compensation network and presents the closed loop transfer
function.
The guidelines for positioning the poles and zeroes and for
calculating the component values are similar to the
guidelines for the Type II network.
1. Choose a value for R
1
, usually between 2k and 5kΩ.
2. Pick a gain (R
2
/R
1
) that will shift the Open Loop Gain up
to give the desired bandwidth. This will allow the 0dB
crossover to occur in the frequency range where the
Type III network has its second flat gain. The following
equation will calculate an R
2
that will accomplish this
given the system parameters and a chosen R
1
.
DBW
∆V
OSC
-
R 2
= --------------
⋅
---------------------
⋅
R 1
V IN
F LC
Figure 11 shows the asymptotic Bode gain plot for the
Type III compensated system and the gain and phase
equations for the compensated system. As with the Type II
compensation network, it is recommended that the actual
gain and phase plots be generated through the use of a
commercially available analytical software package that has
the capability to plot.
The compensation gain must be compared to the open loop
gain of the error amplifier. The compensation gain should
not exceed the error amplifier open loop gain because this is
the limiting factor of the compensation. Once the gain and
phase plots are generated the system may need to be
changed after it is analyzed. Adjust the poles and/or zeroes
in order to shape the gain profile and insure that the phase
margin is greater than 45
o
.
3. Calculate C
2
by placing the zero at 50% of the output
filter double pole frequency:
1
C
2
= ---------------------------------
π
⋅
R
2
⋅
F
LC
4. Calculate C
1
by placing the first pole at the ESR zero
frequency:
C
2
C
1
= ---------------------------------------------------------------------
-
2
⋅
π
⋅
R
2
⋅
C
2
⋅
F
ESR
–
1
5. Set the second pole at half the switching frequency and
also set the second zero at the output filter double pole.
This combination will yield the following component
calculations:
R
1
-
R
3
= ------------------------------
F
SW
------------------- –
1
-
2
⋅
F
LC
1
C
3
= ----------------------------------
-
π
⋅
R
3
⋅
F
SW
5
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