xilinx Synthesizable High PerformanceSynchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. TheVirtex™ series of FPGAs and the Spartan™-II family of FPGAs have many features, such asSelectI/O™ resource and the Clock Delay Lock Loop, that make it easy to interface to highspeed Synchronous DRAMs. This application note describes the design and implementation of a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAMcontroller in the Virtex FPGA family. The design can also be implemented with a Spartan-IIdevice. A 32-bit wide data interface version can run up to 125 MHz when automatically placedand routed in a Virtex -6 speed grade device. Hand placed versions of the design can run evenfaster.
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