Hierarchical Design
Methodology Guide
UG748 (v 14.1 ) April 24, 2012
This document applies to the following software versions: ISE Design Suite 14.1 and later
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Hierarchical Design Methodology Guide
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UG748 (v 14.1 ) April 24, 2012
Revision History
Date
03/01/2011
Version
13.1
Revision
• Added new chapter on Team Design Flow.
• Added new information on:
• Black box support
• ImportTag
• Memory Reduction scheme
•
•
•
•
Under
Partition States,
added information on setting a partition state to
auto.
Added new section
Partitioning Processor Systems.
Added new section
Updated Attributed Value Not Used on Imported Partition.
Indicated where support is limited for some functionality to Virtex®-6, Spartan®-6,
and Xilinx® 7 series FPGA devices only.
• Added new information on
Setting the ImportTag Attribute,
including
Setting the
ImportTag Attribute from the Tcl Console.
• Under
Managing the Preservation Attribute,
corrected command to
Specify Partitions
instead of
Implementation Settings.
Clarified first step in
Exporting PXML Files.
Added information on PREV files in
Exporting Partitions.
Clarified distinction between “top level” and “top partition.”
Added information to section
Floorplan Team Member Blocks to a Specific Region.
07/06/2011
13.2
10/19/2011
13.3
•
•
•
•
01/18/2012
04/24/2012
13.4
14.1
• Added note in Chapter 1, Partitions, explaining that the Stacked Silicon Interconnect
(SSI) technology is not supported in the Xilinx ISE® Design Suite.
• Added new section
Elements to Keep in Top Partition
stating that the only required
element to keep in the Top partition is STARTUP.
• Renamed section
Partitioning Processor Systems
to
Partitioning EDK or System
Generator Systems.
• Added text to section
Partitioning EDK or System Generator Systems
recommending
that you apply a partition to the entire system, rather than to individual peripherals
or blocks.
• Added new section
Keep Hierarchy (KEEP_HIERARCHY) Constraints
recommending that you not use these constraints in a partitioned design.
UG748 (v 14.1 ) April 24, 2012
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Hierarchical Design Methodology Guide
Hierarchical Design Methodology Guide
www.xilinx.com
UG748 (v 14.1 ) April 24, 2012
Table of Contents
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 1: Partitions
PXML Files
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Deciding When to Use Partitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Costs and Benefits of Using Partitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Partition States
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Partition Changes That Require Re-Implementation
. . . . . . . . . . . . . . . . . . . . . . . . . 11
Partition Changes That Do Not Require Re-Implementation
. . . . . . . . . . . . . . . . . 12
Partition Preservation Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Import Location
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Importing With Different Hierarchy
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Managing Memory Usage on Large Designs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Black Box Usage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Partition Context Rules
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 2: Design Considerations
Optimization Limitations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using BoundaryOpt to Optimize IP Cores
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecting the Design
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Achieving the Benefits of an HD Flow
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limitations on Preserving Routing Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floorplanning Partitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partitioning EDK or System Generator Systems
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
24
26
27
29
30
31
Chapter 3: Synthesis Partition Flow
Incremental Synthesis Partition Flow
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Bottom-Up Synthesis Partition Flow
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Synthesis Tools
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chapter 4: Command Line Partition Flow
Xilinx Implementation Tools
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PXML File
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Running Implementation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exporting Partitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Updating Partition State to Import
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Iterative Design
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using SmartXplorer in Partitioned Designs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
44
45
47
48
48
Hierarchical Design Methodology Guide
UG748 (v 14.1 ) April 24, 2012
www.xilinx.com
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